Coherent Logix, Inc.

21st Century Technologies, Inc.

Northrop Grumman Systems Corporation

Craig Michael Chase

Michael B Doerr

David A Gibson

William H Hallidy

James Daniel Snyder, Ii

A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output devices, or mixed combinations of these. In response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device. In response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.

Processing system with interspersed processors and communication elements having improved communication routing

A planning and search system are described wherein a graph search and segment matching are used to handle very large searches at a higher speed.

Segment matching search system and method

Processing system with interspersed processors and communication elements having improved wormhole routing

Stall propagation in a processing system with interspersed processors and communicaton elements

A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

Processing system with interspersed processors using selective data transfer through communication elements

Processing system with interspersed processors and dynamic pathway creation

Processing system with interspersed processors using shared memory of communication elements

Processing system with interspersed processors and communication elements

Processing system with interspersed stall propagating processors and communication elements

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Austin, TX, United States of America

Craig Michael Chase