Kla Tencor Corporation

Craig MacNaughton

Jaydeep K Sinha

Amir Azordegan

Pradeep Vukkadala

Sathish Veeraraghavan

Allen Park

Ellis Chang

Krishna Rao

Prasanna Dighe

Joseph Gutierrez

Wei Chang

Ramon Olavarria

A method to collect data and train, validate and deploy statistical models to predict overlay errors using patterned wafer geometry data and other relevant information includes selecting a training wafer set, measuring at multiple lithography steps and calculating geometry differences, applying a plurality of predictive models to the training wafer geometry differences and comparing predicted overlay to the measured overlay on the training wafer set. The most accurate predictive model is identified and the results fed-forward to the lithography scanner tool which can correct for these effects and reduce overlay errors during the wafer scan-and-expose processes.

Statistical overlay error prediction for feed forward and feedback correction of overlay errors, root cause analysis and process control

A method and apparatus for process control in the processing of a substrate is disclosed in the present invention. Embodiments of the present invention utilize a first analysis tool to determine changes in a substrate's geometry. The substrate geometry data is used to generate sampling plan that will be used to check areas of the substrate that are likely to have errors after processing. The sampling plan is fed forwards to a second analysis tool that samples the substrate after it has been processed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Method and device for using substrate geometry to determine optimum substrate analysis sampling

Methods and systems for determining one or more parameters of a wafer inspection process are provided. One method includes acquiring metrology data for a wafer generated by a wafer metrology system. The method also includes determining one or more parameters of a wafer inspection process for the wafer or another wafer based on the metrology data.

Metrology optimized inspection

Systems and methods for providing improved scanner corrections are disclosed. Scanner corrections provided in accordance with the present disclosure may be referred to as wafer geometry aware scanner corrections. More specifically, wafer geometry and/or wafer shape signature information are utilized to improve scanner corrections. By removing the wafer geometry as one of the error sources that may affect the overlay accuracy, better scanner corrections can be obtained because one less contributing factor needs to be modeled.

Using wafer geometry to improve scanner correction effectiveness for overlay control

Methods and systems enabling ultra-high resolution topography measurements of patterned wafers are disclosed. Measurements obtained utilizing the ultra-high resolution metrology may be utilized to improve wafer metrology measurement accuracies. Additionally, measurements obtained utilizing the ultra-high resolution metrology may also be utilized to provide feedback and/or calibration control to improve fabrication and design of wafers.

Growing community of inventors

Los Gatos, CA, United States of America

Craig MacNaughton