Advanced Micro Devices Corporation

Craig M Peterson

S Doug Ray

An improved power-on reset circuit is provided for controlling reset signal transition until after the power supply has achieved operational levels. Specifically, the reset signal is designated to transition from a high to a low state after the power supply exceeds a fixed reference voltage. The reference voltage is set at a voltage value greater than the operational voltage level of devices within a load circuit connected to the output of the power-on reset circuit. The power-on reset circuit includes numerous subcircuits used to define the reference voltage, trigger the reference voltage in relation to the power supply voltage, delay the triggered voltage, and buffer the delayed, triggered voltage to a reset value capable of driving load circuit impedances.

Low power, slew rate insensitive power-on reset circuit

A reduced noise, low power, high speed output buffer circuit is provided for driving a load. The output buffer circuit utilizes multiple stage pull-up and pull-down transistors. During the time in which the first stage pull-down (or pull-up) transistor is activated, all of the opposing pull-up (or pull-down) transistors are deactivated at substantially the same time. Thereafter, the remaining stages of pull-down (or pull-up) transistors are activated. Delayed turn on in conjunction with rapid turn off achieves low overshoot and undershoot noise transient levels at the power supplies.

Growing community of inventors

Austin, TX, United States of America

Craig M Peterson