National Instruments Corporation

Craig M Conway

Brian Keith Odom

Neil S Feiereisel

Robert Wayne Hormuth

Kevin L Schultz

Bob Mitchell

Glen Sescila

B Keith Odom

Glen O Sescila, Iii

William R Pitts

Ross Sabolcik

M Dean Brockhausen, Jr

Daniel J Baker

Rodney W Cummings

Rafael Castro Scorsi

Scott B Kovner

Eric R Gardiner

Christopher A Clark

Jeff A Bergeron

Gabriel L Narus

Timothy A Stelzer

A system and method for training a data path for parallel data transfer are presented. A first part of the method includes determining a delay setting for each coupling of a plurality of parallel couplings between a first device and a second device. The delay setting for each coupling may substantially align reception of signals transmitted from the first device to the second device on each coupling with a system clock. A second part of the method includes determining the alignment of the plurality of parallel couplings relative to each other. A timing adjustment for one or more of the plurality of parallel couplings may then be determined, whereby after the timing adjustment, signals transmitted from the first device to the second device on the plurality of couplings are received by the second device in alignment with each other.

Training a data path for parallel data transfer

Provided in some embodiment is a computer system, including a first peripheral device, having a first external data input, a first peripheral storage device to store the measurement data, a first peripheral device output to couple to a system interconnect of the computer system. The first peripheral device capable of receiving measurement data via the external data input the first peripheral device capable of transferring at least a portion of the measurement data to a second peripheral device of the computer system via the system interconnect, and where the second peripheral device is capable of processing at least a portion of the measurement data transferred to the second peripheral device.

Peripheral devices integrated into a processing chain

Provided is a method of streaming transfer of data between a plurality of devices of a computer system. The method includes providing data to be sent from a source device to a target device and includes receiving, at the source device, one or more transfer credits from the target device. A transfer credit may be indicative of an amount of data that the target device is authorizing to be sent to the target device. The method also includes determining whether or not an accumulated transfer credit value satisfies a threshold value. If the accumulated transfer credit value satisfies the threshold value, the source device sends data to the target device and modifies the accumulated transfer credit value based on a quantity of data sent. If the accumulated transfer credit value does not satisfy the threshold value the source device does not send data to the target device.

Data movement system and method

A system and method for aligning a local timebase to a remote timebase given a timebase error value from a higher-level protocol, and using the aligned timebases to generate and distribute synchronized events and synchronized adjustable frequency periodic signals across a domain using the aligned timebases. Slightly speeding up or slowing down a periodic signal used to count time, a local timebase may be aligned to a remote timebase when given an error value from a higher-level protocol. A device may be configured to begin generating a periodic waveform at an agreed upon time in the future, once the timebases are aligned, where the time may be synchronized to remote devices via a synchronization protocol and an alignment mechanism. Remote periodic signals may remain synchronized to each other as long as the higher-level protocol and timebase alignment algorithm keep the timebases aligned. A common reference periodic signal may be shared between all devices, and the reference periodic signal or a conditioned version of the reference periodic signal may be specified as the periodic signal to control the operation of the timebase circuitry. The common reference periodic signal may improve synchronization performance beyond the capabilities of the higher-level protocol, and may in addition provide means for synchronization fault tolerance.

Aligning timebases to share synchronized periodic signals

Trigger reception on different instrumentation devices may be synchronized by each instrumentation device generating one or more trigger enable signals and delaying performance of an operation in response to a trigger signal until a transition in a trigger enable signal. An instrumentation system may include several instrumentation devices and a communication medium coupling the instrumentation devices. One of the instrumentation devices may process data in response to a sample clock signal. That instrumentation device may also generate a trigger enable signal and delay performing an operation in response to a trigger signal transmitted via the communication medium until a transition in the trigger enable signal occurs. The trigger enable signal is not the sample clock signal. The trigger enable signal may be synchronized to another trigger enable signal generated by another one of the instrumentation devices.

Synchronizing measurement devices using trigger signals

In some embodiments, a user may select an elemental function such as read, write, or configuration from a graphical programming environment. A file may be created that instantiates functionality into a programmable hardware element to allow it to send a command across a serial protocol to peripheral interface circuitry and ultimately to peripheral chips (e.g., network chips on a CAN). The elemental node concept may be generic to any network chip because the node may contain only the general data of a packet (e.g., command type, value of data bytes, etc). The actual interface to a network chip may be handled inside the peripheral interface circuitry. The peripheral interface circuitry may have the details of the network chip in which it interfaces and may abstract details of the network chip from the target programmable hardware element through the serial protocol.

Implementation of packet-based communications in a reconfigurable hardware element

System and method for synchronizing multiple devices coupled to a system timing module (STM) via respective first transmission media, wherein two or more of the respective first transmission media have different respective transmission times. The STM and devices share a common clock, in phase and with respect to a common reference. Each device is configured to transmit respective signals to the STM within a common clock cycle. Respective delays corresponding to the devices are determined based on the respective transmission times, where the respective delays are applicable to respective signals received from the devices to synchronize received corresponding pulses in the signals to within a common clock cycle. The respective delays are applied to respective signals received from the plurality of devices to synchronize received corresponding pulses in the signals to within the common clock cycle, after which the STM is operable to trigger the devices as a single device.

Coordinating data synchronous triggers on multiple devices

In one embodiment, a system comprises a delay determining unit that may be operable to determine a relative delay between the first signal provided by the first source and the second signal provided by the second source, based upon a travel path of the first signal and a travel path of the second signal. In addition, a delay circuit, comprised within the waveform generator, may be configured to be programmed to delay output of the first signal to output the first signal at a predetermined position with respect to output of the second signal, based on the determined relative delay. More specifically, in one embodiment, the delay circuit may be configured to be automatically programmed to add the relative delay to the output of the first signal to automatically align the output of the first signal with respect to the output of the second signal.

Automatic delays for alignment of signals

System and method for synchronizing multiple instrumentation devices

The coupling apparatus couples two circuit cards to fit into a larger chassis. A coupling element can connect two similar sized circuit cards or two different sized circuit cards together by coupling the first circuit card and the second circuit card to effectively form a combined circuit card of a larger size. The larger size may allow for more features, may make it easier to dissipate heat, may make the circuit cards easier to shield, and/or may allow for the use of larger and less expensive components on the circuit cards.

PXI chassis with backwards compatibility for existing PXI devices

System and method for configuring a second system in a split bridge distributed environment. A host computer system (host) includes a memory operable to store host driver software (drivers) and a CPU operable to execute the drivers. A serial bus couples the host to the second system. The host saves configuration information for the second system. The second system receives user input requesting a power down condition. The drivers enters a quiescent state, generating an indication of a power down condition. The user powers down and reconfigures the second system. The host detects a link down condition between the host and the second system, and monitors a link status between the host and second system. The user powers up the second system. The host detects a link up condition, restores second system configuration, and performs a discovery process on the second system.

System and method for reconfiguring a system coupled to a host computer through a split bridge

A system for generating waveforms may include a memory configured to store a plurality of waveform segments, a plurality of waveform segment queues each coupled to receive waveform segments output by the memory, and a selection unit coupled to each of the waveform segment queues and configured to read waveform segments out of a selected one of the waveform segment queues. Each of the waveform segment queues may be configured to store a series of one or more waveform segments. The selection unit may be configured to access the first waveform segment queue during a first time period and to access the second waveform segment queue if a first trigger occurs.

System and method for generating waveforms using waveform segment queues

A Wide Area Serial PCI system for connecting peripheral devices to a computer. The WASP system includes a host computer system connected through a serial bus to a remote device. The serial bus can range from several meters to several kilometers or more. The host computer system includes a CPU and memory, and also includes a first Peripheral Component Interconnect (PCI) bus, also referred to as the local PCI bus. A primary bridge according to the present invention is coupled to the first PCI bus. The primary bridge includes PCI interface circuitry for interfacing to the first PCI bus. The remote device is located remotely from the computer system and comprises a second or remote PCI bus and one or more peripheral devices coupled to the second PCI bus. The remote device also includes a secondary bridge coupled to the second PCI bus.

System and method for efficiently generating packets on a serial bus in response to parallel bus cycles

A Wide Area Serial PCI system for connecting peripheral devices to a computer. The WASP system includes a host computer system connected through a serial bus to a remote device. The serial bus can range from several meters to several kilometers or more. The host computer system includes a CPU and memory, and also includes a first Peripheral Component Interconnect (PCI) bus, also referred to as the local PCI bus. A primary bridge according to the present invention is coupled to the first PCI bus. The primary bridge includes PCI interface circuitry for interfacing to the first PCI bus. The remote device is located remotely from the computer system and comprises a second or remote PCI bus and one or more peripheral devices coupled to the second PCI bus. The remote device also includes a secondary bridge coupled to the second PCI bus. The secondary bridge includes PCI interface circuitry for interfacing to the second PCI bus. The serial bus is coupled between the primary bridge and the secondary bridge. Each of the primary bridge and secondary bridge include parallel/serial transceivers for converting parallel data generated on the first PCI bus and second PCI bus, respectively, to serial data for transmission on the serial bus and for converting serial data received from the serial bus to parallel data for generation on the first PCI bus and second PCI bus, respectively. The primary bridge and the secondary bridge collectively implement a PCI&mdash;PCI bridge register set.

Growing community of inventors

Leander, TX, United States of America

Craig M Conway