Integrated Device Technology, Inc.

Craig Lindahl

Yongdong Zhao

John R Mick

Yong-Dong Zhao

A matrixed memory array device is disclosed that includes input ports and output ports. Each input port is coupled to a first data bus and each output port is coupled to a second data bus that is different and separate from the first data bus. A memory brick is placed at each cross-point between first data buses and second data buses so as to switchably couple frames of data from input ports to output ports. Each memory brick contains a plurality of eight transistor (8-T) memory cells that can be used to store, erase, read, write, and switchably couple a data bit from the input port to a corresponding output port.

Apparatus and method for matrix memory switching element

A weighted round-robin scheduler includes a round-robin table that stores a plurality of cycle link lists. Each cycle link list includes a head flow identification (FLID) value identifying a first flow of the cycle link list, and a tail FLID value identifying a last flow of the cycle link list. A flow table is provided having a plurality of flow table entries. Each flow table entry is associated with a corresponding flow. Each flow table entry stores a parameter that identifies the weight assigned to the associated flow. A packet queue is associated with each flow table entry, wherein each packet queue is capable of storing a plurality of packets. The weighted round-robin scheduler also includes an idle cycle register having an idle cycle entry corresponding with each of the cycle link lists, wherein each idle cycle entry identifies the corresponding cycle link list as active or idle.

Method of performing weighted round-robin queue scheduling using a dynamic link list and structure for implementing same

A deficit round-robin scheduler including a round-robin table configured to store a plurality of cycle link lists, wherein each cycle link list includes a head flow identification (FLID) value identifying a first flow of the cycle link list, and a tail FLID value identifying a last flow of the cycle link list. A flow table is provided having a plurality of flow table entries, wherein each of the flow table entries is associated with a corresponding flow, and therefore has a corresponding FLID value. A packet queue is associated with each flow table entry, wherein each packet queue is capable of storing a plurality of packets. The deficit round-robin scheduler also included an idle cycle register having an idle cycle entry corresponding with each of the cycle link lists, wherein each idle cycle entry identifies the corresponding cycle link list as active or idle.

Method of performing deficit round-robin scheduling and structure for implementing same

A switch queue predictive protocol (SQPP) includes a packet switching system including: a switch fabric having a cross-point switch, and a plurality of line cards, each coupled to the switch fabric. A cross-point buffer is located at each cross-point of the cross-point switch. The switch fabric also includes a plurality of actual available queue space tables (AAQSTs), each identifying the actual queue space available in a row of the cross-point buffers. Each of the line cards includes an input buffer, an output buffer, and a predicted available queue space table (PAQST) identifying predicted queue space available in a corresponding row of the cross-point buffers. Packet information is transmitted from a source line card to the switch fabric only if available queue space is predicted by the corresponding PAQST. The switch fabric uses the AAQST to update the PAQST after packet information is transmitted to a destination line card.

Switch queue predictive protocol (SQPP) based packet switching technique

A network device may perform traffic policing to determine if incoming data cells are in conformance with policing parameters, including a theoretical arrival time (TAT), for each cell's communication channel. Each cell may have an arrival time according to a timer value. The timer value and TAT may rollover upon reaching a maximum value. The network device may be configured to account for such rollovers when determining cell conformance. For each communication channel, a table entry may include the policing parameters and rollover data. Each entry may also include operations and maintenance (OAM) data. The rollover data indicates the rollover phase relationship between the timer value and TAT parameter for each channel. The rollover data may be updated each rollover phase of the timer, for example as part of an OAM table scan process. The network device may be an Asynchronous Transfer Mode (ATM) traffic policing device or switch.

Timer rollover handling mechanism for traffic policing

Switch queue predictive protocol (SQPP) based packet switching method

Content addressable memory (CAM) devices include CAM arrays that can identify a best match(es) from a plurality of matches when an operation to compare data applied to a CAM array against data entries within the CAM array is performed. This best match identification operation is preferably performed internal to the CAM array. The best match identification operation does not require operations to determine a highest priority match based on the relative physical locations of multiple matching entries that might be identified within the CAM array during a compare operation. The CAM device also does not require that the CAM array(s) therein be sectored into groups of entry locations (e.g., rows) having ordered priorities or that each CAM array within a multi-array CAM device be treated as a respective sector. Entries having identical priority may be entries having the same number of actively masked bits therein.

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McKinney, TX, United States of America

Craig Lindahl