Samsung Electronics Co., Ltd.

Craig Hanson

Hongzhong Zheng

Dimin Niu

Mu-Tien Chang

Sun Young Lim

Indong Kim

Ian A Swarbrick

Jangseok Choi

Michael Bekerman

Chihjen Chang

A memory module that includes a non-volatile memory and an asynchronous memory interface to interface with a memory controller is presented. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

Asynchronous communication protocol compatible with synchronous DDR protocol

A memory module includes: a non-volatile memory; and an asynchronous memory interface to interface with a memory controller. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

A memory system includes: one or more memory modules, each comprising a plurality of memory devices having corresponding write commit policies; and one or more memory controllers coupled to the one or more memory modules, the one or more memory controllers having a configurable write operation protocol to operate with the memory devices according to the corresponding write commit policies.

Memory system and method of controlling the same

A Non-Volatile Dual In-Line Memory Module is disclosed (NVDIMM). The NVDIMM may be installed in a Dual In-Line Memory Module (DIMM) docket. The NVDIMM may include a non-volatile memory. A device driver may intercept a request for a memory address destined for a host memory controller, replace the memory address with a pre-mapped memory address or an alias of the pre-mapped memory address, and send the pre-mapped memory address to the host memory controller, so that the host memory controller generates a target memory address to NVDIMM.

DIMM SSD Addressing performance techniques

A memory module includes a plurality of memory components, an in-memory power manager, and an interface to a host computer over a memory bus. The in-memory power manager is configured to control a transition of a power state of the memory module. The transition of the power state of the memory module includes a direct transition from a low power down state to a maximum power down state.

Self-optimized power management for DDR-compatible memory systems

Example embodiments for descrambling and scrambling a memory channel include executing a training mode for the memory device to discover XOR vectors used by the host system to scramble data. The training mode inputs all zero training data to a scrambling algorithm for all memory locations of the memory device to generate scrambled training data that is transmitted over the memory channel to the memory device. The scrambled training data are equal to the XOR vectors corresponding to those memory locations. The scrambled training data is received over the memory channel by the memory device and stored as the XOR vectors for each corresponding memory location. During a functional mode, the scrambled data is received over the memory channel for a specified memory location and the XOR vector stored for the specified memory location is used to descramble the scrambled data prior to writing to the specified memory location.

XOR-based scrambler/descrambler for SSD communication protocols

A Non-Volatile Dual In-Line Memory Module is disclosed (NVDIMM) (). The NVDIMM () may be installed in a Dual In-Line Memory Module (DIMM) docket (). The NVDIMM () may include a non-volatile memory (). A device driver () may intercept a request for a memory address () destined for a host memory controller (), replace the memory address () with a pre-mapped memory address () or an alias () of the pre-mapped memory address (), and send the pre-mapped memory address () to the host memory controller (), so that the host memory controller () generates a target memory address () to NVDIMM ().

DIMM SSD addressing performance techniques

A protocol that enables communication between a host and an Input/Output (I/O) channel storage device, such as a Dynamic Random Access Memory (DRAM) channel Dual In-Line Memory Module (DIMM) form-factor Solid State Drive (SSD), without the need to know or reverse engineer the encoding applied by the host. The control/status data are written to the storage device by sending a protocol training sequence of known values and storing the associated command/status data in the storage device in the same encoding format as that received from the host. These stored values are used at run time to execute encoded commands received from the host and to report status data to the host in the host-recognizable manner. A memory bank-based buffered configuration stores user data also in the as-received condition to preserve the host-specific encoding. This facilitates exchange of user data between the host memory controller and the storage device over the DRAM channel.

I/O channel scrambling/ECC disassociated communication protocol

A Dual In-Line Memory Module (DIMM) Solid State Drive (SSD) System-on-a-Chip (SoC) () is disclosed. The DIMM SSD SoC () can interoperate with a host memory controller () as though it were a traditional Dynamic Random Access Memory (DRAM) DIMM () with system interconnect skew and on-DIMM skew, even though the DIMM SSD SoC () does not have on-DIMM skew. The DIMM SSD SoC () can include variable delay elements () that can replicate the delay a traditional DRAM DIMM () experiences and that the host memory controller () expects, or a superior delay that minimizes system signal integrity issues, thereby increasing maximum system speed.

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San Jose, CA, United States of America

Craig Hanson