Rambus Inc.

Cryptography Research, Inc.

Other

Intel Corporation

Highlands Corporation

Craig Edward Hampel

Frederick Abbott Ware

Ely K Tsern

Richard Maurice Barth

Richard E Perego

Donald C Stark

Mark A Horowitz

Paul G Davis

Ian P Shaeffer

Kevin S Donnelly

Jared L Zerbe

Alfredo Moncayo

Abhijit Mukun Abhyankar

Steven Cameron Woo

David Nguyen

Matthew Murdy Griffin

James A Gasbarro

Stefanos Sidiropoulos

John Bradly Dillon

Billy Wayne Garrett, Jr

John Eric Linstadt

Scott C Best

Bradley A May

Fredrick A Ware

Todd W Bystrom

Bret G Stott

Chad A Bellows

Thomas J Sheffler

Andrew V Anderson

Wayne S Richardson

Lawrence Lai

Donald Victor Perino

Pankaj Rohatgi

Thomas J Holman

Sami James Saab

Benedict C Lau

Jade M Kizer

Catherine Yuhjung Chen

Abhijit Mukund Abhyankar

Thomas Vogelsang

Bruno Werner Garlepp

Kenneth Lee Wright

Ramprasad Satagopan

Jeffrey D Mitchell

Belgacem Haba

Bohuslav Rychlik

Thomas J Giovannini

Peter D MacWilliams

Roxanne T Vu

Taeksang Song

Qi Lin

Evan Lawrence Erickson

Richard E Warmke

Liang Leon Peng

Elke De Mulder

Arun Vaidyanath

Nancy David Dillon, Legal Representative

Jean-Michel Cioranesco

Winthrop Wu

Fred Ware

Guilherme Ozari De Almeida

Jeremy Cooper

Wai-Yeung Yip

Rodrigo Portella Do Canto

John Yan

Don Stark

Michael P Farmwald

Christopher Haywood

Liji Gopalakrishnan

Yuanlong Wang

Christopher Gori

Karnamadakala Krishnamohan

Nancy David Dillon

By Nancy David Dillon

James A Gasbarre

James A Gasborro

An apparatus and method for flexible metadata allocation and caching. In one embodiment of the method first and second requests are received from first and second applications, respectively, wherein the requests specify a reading of first and second data, respectively, from one or more memory devices. The circuit reads the first and second data in response to receiving the first and second requests. Receiving first and second metadata from the one or more memory devices in response to receiving the first and second requests. The first and second metadata correspond to the first and second data, respectively. The first and second data are equal in size, and the first and second metadata are unequal in size.

Flexible metadata allocation and caching

A memory controller includes an interface to couple to storage class memory (SCM) space and dynamic random access memory (DRAM) space. At least a portion of the DRAM storage space is configured as a cache for the SCM storage space. The interface to receive an incoming tag address for a read operation. Tag comparison circuitry performs a comparison of the incoming tag address to stored tag addresses associated with the DRAM cache. The data in the addressed DRAM cache space is selectively provided directly to the memory controller as first read data based on the results of the comparison.

Memory system with cached memory module operations

Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

Memory system topologies including a memory die stack

Improvements are disclosed for 'leveling' or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK' and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.

Memory system with activate-leveling method

Technologies for securing dynamic random access memory contents to non-volatile memory in a persistent memory module are described. One persistent memory module includes an inline memory encryption (IME) circuit that receives a data stream from a host, encrypts the data stream into encrypted data, and stores the encrypted data in DRAM. A management processor transfers the encrypted data from the DRAM to persistent storage memory responsive to a signal associated with a power-loss or power-down event.

Securing dynamic random access memory (DRAM) contents to non-volatile in a persistent memory module

A multi-host processing system may access memory devices (e.g., memory modules, memory integrated circuits, etc.) via memory nodes having memory controllers. The memory controllers may be configured to use more than one error control scheme when accessing the same memory devices. The selection of the error control scheme may be made based on the interface receiving the memory transaction request. The selection of the error control scheme may be made based on information in the memory transaction request. The selection of the error control scheme may be made based on the fabric physical address and a lookup table or address range registers. The selection of the error control scheme may be made based on the memory device physical address and a lookup table or address range registers.

Dynamically configurable memory error control schemes

A buffer integrated circuit (IC) chip is disclosed. The buffer IC chip includes host interface circuitry to receive a request from at least one host. The request includes at least one command to perform a memory compression operation on first uncompressed data that is stored in a first memory region. Compression circuitry, in response to the at least one command, compresses the first uncompressed data to first compressed data. The first compressed data is transferred to a second memory region.

Compressed memory buffer device

Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.

High-performance, high-capacity memory systems and modules

Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.

Memory error detection

A memory module includes a substrate, plural memory devices, and a buffer. The plural memory devices are organized into at least one rank, each memory device having plural banks. The buffer includes a primary interface for communicating with a memory controller and a secondary interface coupled to the plural memory devices. For each bank of each rank of memory devices, the buffer includes data buffer circuitry and address buffer circuitry. The data buffer circuitry includes first storage to store write data transferred during a bank cycle interval (tRR). The address buffer circuitry includes second storage to store address information corresponding to the data stored in the first storage.

Memory module with reduced read/write turnaround overhead

Space in a memory is allocated based on the highest used precision. When the maximum used precision is not being used, the bits required for that particular precision level (e.g., floating point format) are transferred between the processor and the memory while the rest are not. A given floating point number is distributed over non-contiguous addresses. Each portion of the given floating point number is located at the same offset within the access units, groups, and/or memory arrays. This allows a sequencer in the memory device to successively access a precision dependent number of access units, groups, and/or memory arrays without receiving additional requests over the memory channel.

Multiple precision memory system

Improvements are disclosed for 'leveling' or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK′ and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.

Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value.

System including hierarchical memory modules having different types of integrated circuit memory devices

Growing community of inventors

Los Altos, CA, United States of America

Craig Edward Hampel