Micron Technology Incorporated

Craig E Schneider

Gary R Gilliam

Roland Ochoa

Kacey Cutler

Steve G Renfro

Steven G Renfro

A circuit for a sense amplifier (,) for use with a memory device (,). The circuit includes two devices (,and,) that are controlled by a selector (,). The first device (,) drives the sense amplifier (,) with a first current level. The second device (,) drives the sense amplifier (,) with a second current level, different from the first current level. The selector (,) is coupled to the first and second devices (,and,) so as to selectively couple one of the first and second devices (,and,) to the sense amplifier (,) based on a power supply voltage of the memory device (,).

Memory device with a sense amplifier

A circuit for a sense amplifier (14) for use with a memory device (10). The circuit includes two devices (40 and 42) that are controlled by a selector (44). The first device (40) drives the sense amplifier (14) with a first current level. The second device (42) drives the sense amplifier (14) with a second current level, different from the first current level. The selector (44) is coupled to the first and second devices (40 and 42) so as to selectively couple one of the first and second devices (40 and 42) to the sense amplifier (14) based on a power supply voltage of the memory device (10).

A circuit for a sense amplifier (14) for use with a memory device (10). The circuts includes two devices(40 and 42) that are controlled by a selector (44). The first device (40) drives the sense amplifier (14) with a first current level. The second device (42) drives the sense amplifier(14) with a second current level, different from the first current level. The selector (14) is couple to the first and second devices (40 and 42) so as to selectively couple one of the first and second devices(40and 42) to the sense amplifier (14) based on a power supply voltage of the memory device (10).

An apparatus, system and method for identifying an access mode of a semiconductor memory in a data processing system, characterized by significant reduction of the possibility of erroneous identification of the access mode. A semiconductor memory has an access circuit bank with plurality of selectable circuits only one of which is activated, each selectable circuit respectively associated with a selectable semiconductor memory access mode, the access mode selection typically being accomplished by selectively blowing fuses associated with the corresponding selectable circuits. A semiconductor memory access mode is correctly identified by associating, in response to a test signal for determining the fuse status, the respective activated selectable circuit with its corresponding access mode.

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Boise, ID, United States of America

Craig E Schneider