Advanced Micro Devices Corporation

Globalfoundries Inc.

Craig D Eaton

Anwar Kashem

Pouya Najafi Ashtiani

Daniel William Bailey

Bill K C Kwan

Srikanth Arekapudi

Spencer Montgomery Gold

Ganesh Venkataramanan

Matthew J Amatangelo

Deepesh John

Tsun Ho Liu

Methods and systems are disclosed for training, by a sequencer of a memory interface system, an interface with DRAM. Techniques disclosed comprise scheduling a command sequence, including DRAM commands that are interleaved with one or more CSR commands; executing the scheduled command sequence, wherein the DRAM commands are sent to the DRAM through an internal datapath of the system and the CSR commands are sent to the internal datapath; and training the interface based on exchange of data, carried out by the DRAM commands, including adjustments to an operational parameter associated with the interface.

DRAM specific interface calibration via programmable training sequences

Methods and systems are disclosed for frequency transitioning in a memory interface system. Techniques disclosed include receiving a signal indicative of a change in operating frequency, into a new frequency, in a processing unit interfacing with memory via the memory interface system; switching the system from a normal mode of operation into a transition mode of operation; updating control and state register (CSR) banks of respective transceivers of the system through a mission bus used during the normal mode of operation; and operating the system in the new frequency.

Reducing power consumption associated with frequency transitioning in a memory interface

Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further disclosed that determine, by a microcontroller, based on the phase measurements associated with the chiplet, a delay offset, and that delay, based on the delay offset, the propagation of the clock signal through the distribution tree of the chiplet using a delay unit associated with the chiplet.

Multi-chiplet clock delay compensation

A method and apparatus for training data in a computer system includes reading data stored in a first memory address in a memory and writing it to a buffer. Training data is generated for transmission to the first memory address. The data is transmitted to the first memory address. Information relating to the training data is read from the first memory address and the stored data is read from the buffer and written to the memory area where the training data was transmitted.

Method and apparatus for training memory

Methods and systems are disclosed for calibrating, by a memory interface system, an interface with dynamic random-access memory (DRAM) using a dynamically changing training clock. Techniques disclosed comprise receiving a system clock having a clock signal at a first pulse rate. Then, during the training of the interface, techniques disclosed comprise generating a training clock from the clock signal at the first pulse rate, the training clock having a clock signal at a second pulse rate, and sending, based on the generated training clock, command signals, including address data, to the DRAM.

Variable tick for DRAM interface calibration

Methods, systems, and apparatuses are presented that remove BIST intrusion logic from critical timing paths of a microcircuit design without significant impact on testing. In one embodiment, BIST data is multiplexed with scan test data and serially clocked in through scan test cells for BIST testing. In another embodiment, BIST data is injected into the feedback path of one or more data latches. In a third embodiment, BIST data is injected into the result data path of a multi-cycle ALU within an execution unit. In each embodiment, BIST circuitry is eliminated from critical timing paths.

Avoiding BIST and MBIST intrusion logic in critical timing paths

A clock generator system () includes a phase locked loop (PLL) (), a first clock generator (), and a second clock generator (). The PLL () includes a first output configured to provide a first clock signal at a first frequency and a second output configured to provide a second clock signal at the first frequency. The second clock signal is out-of-phase with the first clock signal. An output of the first clock generator () is configured to provide a first generated clock signal whose effective frequency is based on both the first and second clock signals and a first mode signal. An output of the second clock generator () is configured to provide a second generated clock signal whose effective frequency is based on both the first and second clock signals and a second mode signal.

Techniques for integrated circuit clock management using multiple clock generators

A processor () includes a clock source (), a central processing unit (CPU) (), and a clock generator (). The clock source () includes an output for providing a periodic clock signal. The CPU () includes an input for receiving a CPU clock signal. The clock generator () includes a first input coupled to the output of the clock source (), a second input for receiving a mode signal that indicates an output frequency, and an output coupled to the input of the CPU (). The clock generator () provides the CPU clock signal using periodic pulse skipping such that the CPU clock signal has a number of transitions over a unit of time corresponding to the output frequency.

Techniques for integrated circuit clock management using pulse skipping

A method for producing a plurality of clock signals. The method includes generating a reference clock signal using a phase locked loop (PLL). The reference clock signal is then provided to each of a plurality of clock divider units which each divide the received reference clock signal to produce a corresponding divided clock signal. The method then removes one or more clock cycles (per a given number of cycles) in order to produce a plurality of domain clock signals each having an effective frequency based on a frequency and a number of cycles removed from the correspondingly received divided clock signal.

Method and apparatus for clock cycle stealing

A clock generator () includes a first circuit () and a second circuit (). The first circuit () includes a first clock input configured to receive a first clock signal at a first frequency, a second clock input configured to receive a second clock signal at the first frequency, and an output. The second clock signal is out-of-phase with the first clock signal. The second circuit () is coupled to the first circuit () and includes a mode signal input configured to receive a mode signal. The output of the first circuit () is configured to provide a generated clock signal whose effective frequency is based on the first and second clock signals and the mode signal.

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Austin, TX, United States of America

Craig D Eaton