Intel Corporation

Craig D Cedros

Greg A Peek

Nelson L Yaple

Phil W Martin

Dave Chalupsky

Dick Reohr, Jr

An apparatus for interfacing a memory with a bus in a computer system is described. The memory has a data path width which is different than the data path width of the bus. The apparatus comprises a first and a second buffer, a first and a second address generation circuit, and a control circuit. The first buffer is for storing a first portion and a second portion of a first data read from the memory during a read operation which are to be sent to the bus in parallel. The first address generation circuit is for receiving a first address from the bus during the read operation and generating a first memory address to address the memory for the first portion of the first data and a second memory address to address the memory for the second portion of the first data. The second buffer circuit is for storing a second data received from the bus during a write operation. The second address generation circuit is for receiving a second address from the bus for writing the second data into the memory during the write operation, and for generating a third memory address to write a third portion of the second data to the memory and a fourth memory address to write a fourth portion of the second data to the memory. During the read operation, the control circuit causes (1) the first address generation circuit to generate the first memory address and the first buffer to receive the first portion of the first data, and then (2) the first address generation circuit to generate the second memory address and the first buffer to receive the second portion of the first data. During the write operation, the control circuit causes (3) the second address generation circuit to generate the third memory address and the second buffer to send the third portion of the second data, and then (4) the second address generation circuit to generate the fourth memory address and the second buffer to send the fourth portion of the second data.

System for interfacing first and second components having different data

A method and apparatus to optimize buffer memory management in a computer system communications resource. The present invention decreases the time for receiving data from and transmitting data to a network by providing for receipt and transmittal of a data packet, prior to the data packet being in a communications resource buffer memory. Consequently, data spends less time in the communications resource buffer memory. This allows a communications resource to handle more data without increasing the size of its buffer memory and to increase the effective data transfer rate. The present invention provides a means for: 1) starting the transmission of data into the network before all data has been transferred to buffer memory in the communications resource, 2) beginning the transfer of data from the buffer memory of the communications resource before the complete data packet has been received and stored in buffer memory, and 3) error checking to insure data integrity.

System for transferring portion of data to host from buffer if size of

A circuit and processing logic is used to test, configure, and control the operation of computer system resource addressing control signals. The programmable circuit of the present invention determines when, in an I/O access cycle, the resource addressing control (IOCHRDY) signal should be activated by an I/O mapped system resource. The present invention includes lost circuitry for determining whether a particular system resource operates best in a late IOCHRDY mode or an early IOCHRDY mode. The test logic will force the IOCHRDY signal to remain active for an extended period of time. By extending the deactivation time of the IOCHRDY signal far beyond the time at which the deactivation would normally occur, the responsiveness of a command strobe (IORD/IOWR) may be tested. If the deactivation of the command strobe IORD/IOWR follows the extended deactivation time of the IOCHRDY signal, the command strobe (IORD/IOWR) is properly responsive to the IOCHRDY signal and proper operation of the I/O access control logic is verified. If, however, the extended activation of the IOCHRDY signal causes the command strobe (IORD/IOWR) to deactivate prior to the deactivation of the IOCHRDY signal, a nonresponsive command strobe (IORD/IOWR) signal is present and thus a failure condition is detected. A processor-readable bit in a control register indicates a successful or unsuccessful IOCHRDY test condition.

Addressing control signal configuration in a computer system

A circuit and a related process are utilized in a computer system for testing and configuring the width of various portions of memory in a memory array. The circuit captures a state of a memory width control signal (MEMCS16) during a test and configuration cycle, retains the state of the MEMCS16 signal for various blocks of memory, and controls the state of the MEMCS16 signal when a memory access to a particular memory block is made. The circuit tests the state of the MEMCS16 signal for various blocks of the system memory map and thereafter configures a memory control register appropriately. The state of the MEMCS16 signal is retained by a latch when a particular 128K region is accessed and a valid address is present on the address lines. The output of the latch is provided as a processor-readable test result in a bit of a control/test register.

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Beaverton, OR, United States of America

Craig D Cedros