Mips Computer Systems, Inc.

Silicon Graphics, Incorporated

Craig C Hansen

Christopher Rowen

Thomas J Riordan

Danny L Freitas

Steven A Przybylski

Larry B Weber

An apparatus for temporarily disabling a translation lookaside buffer in a computer system upon the occurrence of certain predefined system conditions. Such conditions may be of a first type which have been predetermined to indicate a greater risk that two or more virtual addresses stored in the TLB will simultaneously match the incoming virtual address, and/or of a second type in which access to the TLB is not needed. An example of the first type is a reference to an unmapped segment of memory. An example of the second type is the processing of a non-memory-access instruction. The apparatus may further include failsafe circuitry to shut down the TLB if at least a given number of matches occur at any time and for any reason, the given number being greater than 1. The apparatus prevents loss of data or damage to the chip where match comparisons are performed in parallel.

Translation lookaside buffer shutdown scheme

Apparatus for temporarily disabling a translation lookaside buffer in a computer system upon the occurrence of certain predefined system conditions. Such conditions may be of a first type which have been predetermined to indicate a greater risk that two or more virtual addresses stored in the TLB will simultaneously match the incoming virtual address, and/or of a second type in which access to the TLB is not needed. An example of the first type is a reference to an unmapped segment of memory. An example of the second type is the processing of a non-memory-access instruction. The apparatus may further include failsafe circuitry to shut down the TLB if at least a given number of matches occur at any time and for any reason, the given number being greater than 1. The apparatus prevents loss of data or damage to the chip where match comparisons are performed in parallel.

A CPU or other function unit is disclosed which follows one data ordering scheme internally, and in which incoming and/or outgoing data pass through a data order conversion unit for adapting it to a selectable external data ordering scheme. The means for specifying the external data ordering scheme is accessible from outside the physical package(s) in which the functional unit is housed. The data order conversion unit may comprise a load aligner and/or a store aligner, one or both of which may comprise means for shifting informational units of a smaller size within informational units of a larger size. The shift amount may derive from the low order address bits and may be altered depending on the external data ordering means selected.

Dual byte order computer architecture a functional unit for handling

In data processing systems of the type operable to perform floating point computations there is provided a method, and apparatus implementing that method, for predicting, in advance of the floating point computation, whether or not the computation will produce a floating point exception (e.g., overflow, underflow, etc.). The prediction method includes the steps of combining the exponent fields of the operands of the computation in a manner dictated by the type of operation (i.e., add, subtract, multiply, etc.), and comparing that combination, together with an indication of the computation to be performed (e.g., add, substract, multiply, or divide), to obtain an indication of the possibility of the computation ending in a floating point exception. If an exception is predicted, the indication can be used to halt other data processing operations until completion of the computation so that, in the event the computation actually results in a floating point exception, the handling of the exception can be accomplished with a minimum of effort.

Method and apparatus for precise floating point exceptions

In a RISC device a set of four instructions are provided which allow either the loading or the storage of an unaligned reference. The instructions are overlapped to reduce the overall execution time of the device. A circuit is also provided for executing the instruction set.

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Craig C Hansen