International Business Machines Corporation

Globalfoundries Inc.

Craig Brian Stunkel

Peter H Hochschild

Monty Montague Denneau

Philip Heidelberger

Jay Robert Herring

Dong Chen

Alan Frederic Benner

Derrick LeRoy Garmire

Kevin J Reilly

Bruce D Gavril

Michael K Gschwind

Valentina Salapura

Paul William Coteus

Michael A Blocksome

Alan G Gara

Joseph D Ratterman

Adam James Muff

Bulent Abali

Ramakrishnan Rajamony

Todd Edward Takken

Eugen Schenfeld

Martin Ohmacht

Bruce Martin Fleischer

Alexandre E Eichenberger

Thomas M Gooding

Robert William Wisniewski

John A Gunnels

Mark Edwin Giampapa

Burkhard Steinmacher-Burow

Kathryn Mary O'Brien

Mark Gregory Megerian

Matthias Augustin Blumrich

Sameh W Asaad

Shawn Anthony Hall

John Kevin O'Brien

Thomas Winters Fox

Chen-Yong Cher

Barry Marshall Trager

Peng Wu

Robert Francis Bartfai

Charles David Wait

Sameer Kumar

James Anthony Marcella

George L Chiu

Todd Alan Inglett

Krishnan Sugavanam

Peter A Walker

Gerard Vincent Kopcsay

Jeffrey John Parker

Robert Matthew Senger

Noel A Eisley

David L Satterfield

Douglas R Miller

Rudolf Adriaan Haring

Amith R Mamidala

Yutaka Sugawara

Kristan D Davis

Jose R Brunheroto

Michael B Mundy

Matthew Roger Ellavsky

Nicholas P Rash

Robert E Walkup

James Lee Van Oosten

Samuel J Miller

Ruth Janine Poole

Gabor J Dozsa

Francis Alfred Kampf

Ralph E Bellofatto

Peter Boyle

Brant L Knudson

Norman Christ

Kahn C Evans

William Maupin Stockdell

Alfred Thomas Watson, Iii

Brian E Smith

Donald G Grice

Rajeev Sivaram

Robert Frederick Stucke

Harish Sethu

Cyriel Johan Agnes Minkenberg

A computer network architecture includes a plurality N of first nodes, each first node having kports to a cluster network, where N and kare integers greater than 0; and a local network switch connected to each of the plurality of first nodes, but not to the cluster network. Each first node has kports to the local network switch, where k, is an integer greater than 0, and any two first nodes in the plurality of first nodes communicate with each other via the local network switch or via the cluster network.

Network architecture with locally enhanced bandwidth

An apparatus includes a collective switch hardware architecture, including an input arrangement circuit including multiple input ports and multiple outputs. The input arrangement circuit routes its multiple input ports to selected ones of its outputs. The collective switch hardware architecture includes collective reduction logic coupled to the multiple outputs of the input arrangement circuit and having multiple outputs. The collective reduction logic includes ALU(s) and arbitration and control circuitry. The ALU(s) and arbitration and control circuitry support multiple simultaneous collective operations from different collective classes, and support arbitrary input port and output port mapping to different collective classes. The collective switch hardware architecture further includes an output arrangement circuit including a multiple inputs coupled to the multiple outputs of the collective reduction logic and including multiple output ports. The output arrangement circuit is configured to route its multiple inputs to selected ones of its output ports.

Network switch architecture supporting multiple simultaneous collective operations

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.

Multi-petascale highly efficient parallel supercomputer

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

A computing system includes: a plurality of tightly coupled processing nodes; a plurality of circuit switched networks using a circuit switching mode, interconnecting the processing nodes, and handling data transfers that meet one or more criteria; and a plurality of electronic packet switched networks, also interconnecting the processing nodes, handling data transfers that do meet the at least one criteria. The circuit switched networks and the electronic packet switched networks operate simultaneously.

Dual network types solution for computer interconnects

Briefly, according to an embodiment of the invention, a computing system comprises: a plurality of tightly coupled processing nodes; a plurality of circuit switched networks using a circuit switching mode, interconnecting the processing nodes, and for handling data transfers that meet one or more criteria; and a plurality of electronic packet switched networks, also interconnecting the processing nodes, for handling data transfers that do meet the at least one criteria. The circuit switched networks and the electronic packet switched networks operate simultaneously. The system additionally comprises a plurality of clusters which comprise the processing nodes, and a plurality of intra-cluster communication links. The electronic packet switched networks are for handling collectives and short-lived data transfers among the processing nodes and comprises one-tenth of the bandwidth of the circuit switched networks.

The interconnecting network for switching data packets, having data and flow control information, comprises a local packet switch element (S) with local input buffers (I() . . . I(,y)) for buffering the incoming data packets, a remote packet switch element (S) with remote input buffers (I() . . . I(,y)) for buffering the incoming data packets, and data lines (L) for interconnecting the local and the remote packet switch elements (S, S). The interconnecting network further comprises a local and a remote arbiter (A, A) which are connected via control lines (CL) to the input buffers (I() . . . I(,y), I() . . . I(,y)), and which are formed such that they can provide that the flow control information is transmitted via the data lines (L) and the control lines (CL).

Interconnecting network for switching data packets and method for switching data packets

A method is provided for selecting a data source for transmission on one of several logical (virtual) lanes embodied in a single physical connection. Lanes are assigned to either a high priority class or to a low priority class. One of six conditions is employed to determine when re-arbitration of lane priorities is desired. When this occurs a next source for transmission is selected based on a the specification of the maximum number of high priority packets that can be sent after a lower priority transmission has been interrupted. Alternatively, a next source for transmission is selected based on a the specification of the maximum number of high priority packets that can be sent while a lower priority packet is waiting. If initialized correctly, the arbiter keeps all of the packets of a high priority packet contiguous, while allowing lower priority packets to be interrupted by the higher priority packets, but not to the point of starvation of the lower priority packets.

Priority arbitration mechanism

The invention is a replication method that requires only one copy of a packet entering a multiport switch to be transmitted from the input port, the method acquiring the deadlock avoidance advantages of virtual cut-through operation. The goal is achieved via a central buffer, with replication occurring during the read of the chunk out of the central buffer by the output ports.

Multicasting using a wormhole routing switching element

A method for substantially preventing routing deadlocks and reliably routing service messages in a network comprised of successive stages of cross-point switches which collectively interconnect a plurality of nodes external to the network, wherein at least one service message is carried between one of the nodes and one of the cross-point switches over a route through the network, including the steps of defining a plurality of routes through the network such that at least one service message can be carried from individual nodes within the plurality of nodes over different corresponding ones of the routes to every cross-point switch within the network, wherein each of the defined routes extends over at least one link; duplicating a message to be routed through the network; and imposing routing restrictions on at least one of the cross-point switches in the network.

Method for deadlock free and and reliable routing in a packet switched

A quiesced and synchronous distributed data processing system includes a primary node, a secondary node and a switch between the primary and secondary nodes. The TOD for the primary node is set depending on the system. The invention sets the TOD for the switch based on the TOD of the primary node. The primary node then verifies the switch TOD. If verified, the TOD for the secondary node is set, based on the TOD of the primary node. Finally, the secondary node self-verifies its TOD.

Verifying a time-of-day counter

A method for adaptive routing of messages in a computer network. The method provides adaptive source routing by generating at a source node a routing message describing a plurality of allowable paths via which data message can reach a desired destination. The data message and the routing message are sent by the source to a first switch, and the routing message is evaluated by control logic to determine if an available, allowable path exists. If so, the data message and routing message are sent via that path to the destination.

System for adaptively routing data in switching network wherein source

Connections between the node switch sets associated with processors in large scalable processor arrays, such as those of the butterfly variety, are arranged, like the 2-D mesh array, in rows and columns between the node switch sets. Additional sets of switches called pivot switch sets are used to accomplish this. They are added to the processors and the processor switch sets to form processor clusters. The clusters are each assigned a logical row and column location in an array. Each pivot switch set is connected to all node switch sets in the same assigned column location and to all node switch sets in the same assigned row location as the pivot set. Consequently, any two node switch sets are connected by way of a pivot set located at either (a) the intersection row of the first node set and the column of the second node set or at (b) the intersection of the column of the first node set and the row of the second node set.

Scalable switch wiring technique for large arrays of processors

Apparatus and an accompanying method for establishing deadlock-free routing in a large bi-directional multi-stage inter-connected cross-point based packet switch, particularly, though not exclusively, that employed within a high speed packet network of a massively parallel processing system (400). Specifically, in selecting routes for inclusion within route tables (320, 360, 380) contained within the system, the entire network is effectively partitioned such that certain routes would be prohibited in order to isolate packet traffic that would flow solely between nodes in one partition, e.g. system half (503), of the system from packet traffic that would flow between nodes in the other partition, e.g. another system half (507). In that regard, to pick routes for packets that are to transit between nodes situated in a common partition of the system, those routes that contain a path(s) (524, 544) passing through the other system partition would be prohibited. No such route prohibition would occur in selecting a route that is to carry a packet between nodes in multiple system partitions, e.g. between different halves of the system.

Technique for accomplishing deadlock free routing through a multi-stage

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Bethel, CT, United States of America

Craig Brian Stunkel