Marvell Asia Pte., Ltd.

Cavium, Inc.

Craig Barner

Richard Eugene Kessler

David Asher

Isam Wadih Akkawi

Thomas Frederick Hummel

Bradley D Dobbie

Daniel Edward Dever

Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.

Low latency inter-chip communication mechanism in a multi-chip processing system

Low latency inter-chip communication mechanism in multi-chip processing system

In an embodiment, a method includes receiving at a data interface a data stream having a plurality of logical communication channels. The data stream includes in succession a first data burst corresponding to one of the plurality of logical communication channels, a burst control word and a second data burst corresponding to the one or an other of the plurality of logical communication channels. The burst control word includes a first error check that protects the first data burst and the burst control word and a second error check that protects only the burst control word. The first error check and the second error check are examined. Only the one logical communication channel is errored out if the first error check is bad and the second error check is good; all open logical communication channels are errored out if the first error check is bad and the second error check is bad.

Bit error rate impact reduction

In an embodiment, a method for determining a word boundary in an incoming data stream includes initializing an N bit register with initial content, receiving a number of consecutive N bit words of the incoming data stream and processing each of the number of consecutive N bit words. The processing includes performing operations per bit position of the register, including performing an XOR operation on a corresponding received data bit and a next received data bit, performing an AND operation on a current state of the bit position of the register and a result of the XOR operation, and storing a result of the AND operation to update the state of the bit position of the register. The word boundary is defined based on the content of the register following the processing of the number of consecutive N bit words.

Word boundary lock

Growing community of inventors

Shrewsbury, MA, United States of America

Craig Barner