Intel Corporation

Craig B Peterson

David G Carson

George W Cox

David B Johnson

David L Budde

John L Wipfli

Anthony L Cornish

William L Bain, Jr

Gurbir Singh

Robert C Duzett

Brad W Hosler

Shekhar Yeshwant Borkar

James A Sutton, Ii

Linda J Rankin

Jerry G Jex

Keith M Self

Charles E Dike

Doran K Wilde

John A Urbanski

John A Bayliss

Justin R Rattner

David W Archer

Keith-Michael W Self

Jim Sutton

Robert Gatlin

Artur H Lederhofer

Marcos De Oliveira Camargo

Scott A Ogilvie

Robert C Bedichek

Gerhard Grassl

A computer system having at least a first microprocessor for processing information and a first memory coupled to the first microprocessor via a first point-to-point interface. The first point-to-point interface provides communication of signals between the first microprocessor and the first memory irrespective of the phase of the signals received by either the first microprocessor or the first memory. The first point-to-point interface includes a first point-to-point circuit in the microprocessor for receiving the signals from the first memory. The first point-to-point circuit and the microprocessor comprise a single integrated circuit in some implemented embodiments, providing ease of construction and design of systems having a variety of topologies. A second microprocessor may also be coupled to the first memory via a second point-to-point interface, the first microprocessor and the second microprocessor sharing the first memory for storage of information used by the first microprocessor and the second microprocessor. In this configuration, the first memory may include a duplicate cache store for the first microprocessor and the second microprocessor, in order to provide cache consistency for the two processors. The system may also include a first input-output device coupled via a second point-to-point interface to the first memory. A variety of topologies of processors, memories and input/output devices may be designed into 'clusters' wherein each cluster communicated with one another for accesses, remote and local, for accessing input/output devices, and for maintaining cache consistency.

Microprocessor point-to-point communication

An asynchronous interface enabling a processor node operating at a first clocking frequency to transfer and receive information from a communications network operating at a second clocking frequency. The asynchronous interface comprises an input synchronizer and an output synchronizer. The input synchronizer asynchronously receives a first plurality of information packets from the processor node and synchronously transfers the first plurality of information packets into the communications network. The output synchronizer, however, synchronously receives a second plurality of information packets from the communications network and asynchronously transfers the second plurality of information packets into the processor node. Both the input and output synchronizers are coupled between the communications network and the processor node.

Asynchronous interface between parallel processor nodes

An I/O processor includes an execution unit (EU), a register file, an I/O bus sequencer and a local bus sequencer. The EU decodes an ACCESS instruction having a pointer to a parameter register comprised of: a number of fields for storing a sequencer code identifying one of the sequencers; a logical byte specifying a location in memory to be addressed and valid and block bits; a reply register set pointer to a register set in the register file designated to receive a reply to the ACCESS instruction; and, a length field specifying the location and length of a data block in the register file from which data is to be obtained. A data pointer is generated by taking the logical byte in the parameter register and passing it through a register set mapper to produce a register file physical address. The valid bit of the logical byte is turned off as it is translated by the register the mapper so that the bus sequencer can take control over the corresponding register set. The block bit is set upon the condition that the ACCESS instruction attempts to access a register set whose valid bit is not set, and the block bit is reset upon the condition that the task which is executing the ACCESS instruction attempts to access a register set whose block and valid bits are set.

Multi-tasking register set mapping system which changes a register set

An I/O processor for controlling data transfer between a local bus and an I/O bus. An Execution Unit, an I/O bus sequencer, and a local bus sequencer are connected to a register file. The register file is uniformly addressed and each of the Execution Unit, the local bus sequencer, and the I/O bus sequencer have read/write access to the register file. The register file is comprised of a plurality of register sets. The Execution Unit includes a programmed processor which is programmed to allocate the register sets among tasks running on the processor by passing register-set descriptors between the tasks in the form of messages. The local bus sequencer includes a packet-oriented multiprocessor bus, there being a variable number of bytes in each of the packets. The I/O sequencer includes logic for multibyte sequencing of data at a bus-dependent data rate between the I/O bus and the register file. Each of the tasks includes a task frame, each task frame including register-set pointers. The register-set pointers map between logical addresses used in the instructions of the tasks used to access the pointers and physical register-set addresses used to access the register. Programmed logic in each of the Execution Unit, the local bus sequencer, and the I/O bus sequencer dynamically allocate the register sets to the sending and destination tasks.

Memory-based interagent communication mechanism

An I/O bus sequencer for providing a data path between an execution Unit (EU-10), a register file (14) and devices connected to a bus (28). A programmable logic array (PLA-18) stores a program which controls a service table (20). The service table includes a plurality of entries divided into fields. One of the fields when decoded instructs the PLA as to what kind of operation the bus sequencer is to perform. Line selection (priority) logic (22) connected to I/O request lines (30) and to the service table (20) determines which service table entry the PLA is to use. A bus interface connected to the I/O bus ports (26) and to the PLA (18) routes data between the I/O bus ports (26) and the register file (14), entries of which are controlled by use of register sets. The service table fields include register set descriptors for storing the status of register set buffers. The PLA decodes an ACCESS instruction to start an operation by loading the first register set descriptor, and then decodes sequential SUPPLY instructions to the entry. Each SUPPLY instruction loads an empty register set descriptor field to be used when the current register set descriptor field is exhausted.

Programmable I/O sequencer for use in an I/O processor

A number of intelligent nodes (bus interface units-BIUs and memory control units-MCUs) are provided in a matrix composed of processor buses (105) with corresponding error-reporting and control lines (106); and memory buses (107) with corresponding error-reporting and control lines (108). Error-detection mechanisms deal with information flow occuring across area boundaries. Each node (100, 101, 102, 103) has means for logging errors and reporting errors on the error report lines (106, 108). If an error recurs the node at which the error exists initiates an error message which is received and repropagated on the error report lines by all nodes. The error message identifies the type of error and the node ID at which the error was detected. Confinement area isolation logic in a node isolates a faulty confinement area of which the node is a part, upon the condition that the node ID in an error report message identifies the node as a node which is a part of a faulty confinement area. Logic in the node reconfigures at least part of the system upon the condition that the node ID in the error report message identifies the node as a node which is part of a confinement area which should be recofigured to recover from the error reported in the error report message.

Apparatus for recovery from failures in a multiprocessing system

A number of intelligent nodes (bus-interface units-BIUs and memory-control units-MCUs) are provided in a matrix composed of processor buses (105) with corresponding error-reporting and control lines (106); and memory buses (107) with corresponding error-reporting and control lines (108). Each node (100, 101, 102, 103) has means for logging errors and reporting errors on the error-report lines (106, 108). Processor modules (110) and memory modules (112) are each connected to a node which controls access to a common memory bus (107). Each node includes means (a married bit-170 and a shadow bit-172) for marrying modules in pairs such that each module in the pair tracks the operations directed to the module pair, and each module in the pair alternates with the other module in the handling of requests or replies. Each node registers the ID of the other node in a spouse ID register. Comparison logic (162, 164) in each node resets the married bit upon the condition that the node ID (identifying the node at which the error occurred) in an error-report message is equal to the ID stored in the spouse ID register, thus identifying the spouse node (the partner of the node in which the comparison logic is located) as the source of the error. Resetting the married bit splits apart the primary/shadow pair, so that the error-free module takes over and ceases to alternate with its partner.

Apparatus for redundant operation of modules in a multiprocessing system

A number of intelligent crossbar switches (100) are provided in a matrix of orthogonal lines interconnecting processor (110) and memory control unit (MCU) modules (112). The matrix is composed of processor buses (105) and corresponding error-reporting lines (106); and memory buses (107) with corresponding error-reporting lines (108). At the intersection of these lines is a crossbar switch node (100). The crossbar switches function to pass memory requests from a processor to a memory module attached to an MCU node and to pass any data associated with the requests. The system is organized into confinement areas at the boundaries of which are positioned error-detection mechanisms to deal with information flow occurring across area boundaries. Each crossbar switch and MCU node has means for the logging and signaling of errors to other nodes. Means are provided to reconfigure the system to reroute traffic around the confinement area at fault and for restarting system operation in a possibly degraded mode.

Apparatus of fault-handling in a multiprocessing system

A microprocessor receives addresses and data from a peripheral subsystem for use in subsequently accessing portions of the main memory of a data processing system in a controlled and protected manner. Each of the addresses is used to interrogate an associative memory to determine if the address falls within one of the subranges for a 'window' on the main memory address space. If the address matches, then it is used to develop a corresponding address on the main memory address space. The data associated with the peripheral subsystem address is then passed through the interface and into the main memory at the translated memory address. Data transfer is improved by buffering blocks of data on the microprocessor. Data bytes are written into the buffer at a slower rate than data blocks are read out of the buffer and into main memory. A buffer bypass register allows single bytes of data to be transferred to a single address by bypassing the buffer. Address development and memory response signals are generated by the microprocessor rather than the peripheral subsystem processor for block transfers.

Microprocessor providing an interface between a peripheral subsystem and

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Portland, OR, United States of America

Craig B Peterson