Unisys Corporation

Sperry Corporation

Craig B Johnson

Carl R Crandall

Haeng D Park

Michael C Otto

Michael J Heideman

Joseph E Kessler

Thomas N DeVries

Dennis R Konrad

Thomas P Cooper

David A Novak

James W Adcock

Mitch M Maurer

Benjamin T George

Kathleen Georgia Elliot

Vladi Pusic

Yonghe Liu

Monte E Smith

Kenneth L Willis

Robert S Yach

The various embodiments of the invention relate to analyzing operations of an emulated input-output processor. Instructions native to the first type of instruction processor are emulated on a second-type instruction processor. The instruction processor emulator executes an operating system that includes instructions native to the first type of instruction processor. The operating system includes instructions that write input/output (IO) requests to the memory arrangement in response to IO functions invoked by a program. An IOP emulator that is executable on the second-type processor emulates IOP processing of IO requests from the memory arrangement. The IOP emulator maintains in the memory arrangement a first set of data structures used in processing the IO requests. State data currently contained in the data structures is stored on a retentive storage device, and in response to user input controls, the state data is read from retentive storage and displayed.

Offline emulated input/output processor debugger

An apparatus for and method of implementing a cluster lock processing system having a relatively large number of commodity cluster instruction processors which are managed by a highly scalable, off the shelf communication processor. Because the commodity processors have virtually no system viability features such as memory protection, failure recovery, etc., the communication processor assumes the responsibility for providing these functions. The low cost of the commodity cluster instruction processors makes the system almost linearly scalable. Furthermore, having a fully scalable communication processor ensures a completely scalable system. The cluster/locking, caching, and mass storage accessing functions are fully integrated into a single hardware platform.

Standard channel I/O processor (SCIOP)

A system and method for testing I/O components without requiring initiation of the test I/O requests from the operating system via the instruction stream. An I/O system facilitates I/O operations between a processing system and I/O devices during normal I/O processing. An exerciser initiation queue is established, which corresponds to an operating initiation queue used during normal I/O processing. The I/O system is configured to monitor for test I/O requests on the exerciser initiation queue in lieu of monitoring for standard I/O requests on the operating initiation queue. A testing module enters the test I/O requests on the exerciser initiation queue in a format analogous to standard I/O requests entered on the operating initiation queue during normal I/O processing. The test I/O requests on the exerciser initiation queue are processed via the I/O system. Upon I/O completion, status may be returned to the testing module for processing of test results.

System and method for performing input/output diagnostics

A system and method for processing I/O requests in a computing system. I/O packets are created via an operating system associated with the computing system, where the I/O packets include I/O transaction information. The I/O packets are made accessible to an I/O system. A command for a channel type connecting a target I/O component to the I/O system is constructed, where this command construction is based on the I/O transaction information provided in the I/O packet, and based on physical aspects of the target I/O component and channel type provided independently of the I/O packet. The constructed command is issued to the target I/O component in accordance with the channel type.

System and method for facilitating use of commodity I/O components in a legacy hardware system

A disk cache translation system for mapping data record lengths between systems having different data record lengths. Command queue ( ) maps into initiation queue ( ) to allow I/O manager ( ) to manage I/O requests from operating system ( ). I/O requests are statused by I/O manager ( ) using status queue ( ). Store-thru cache ( ) provides a single interface to disk array ( ) such that disk array write operations are reported complete only when user memory ( ), I/O cache ( ) and disk array ( ) are synchronized. Data record length translations are performed using I/O cache ( ) in order to align data record length differences between operating system ( ) and I/O device ( ).

Method and apparatus for disk cache translation between systems

A procedure, enabled in software, and applied to a cache/disk environment controlled by a host computer operating through a Block Multiplexor Channel Interface and Storage Control Unit, functions to use FIPS 97 and FIPS 60 protocols to execute data transfers between host processors and a plurality of disks whereby simultaneous operations can function with up to 16 disk units. Up to seen I/O requests can be queued on each of the 16 disk units while the system can normally operate in the cache/disk mode. Additionally, the system can operate in the disk-only mode or storethrough mode.

FIP-compliant block multiplexor channel interface operational method for

A data processing system has a host processor, a RAM, a cache memory for storing segments of data, a plurality of disk drive devices and a storage control unit for controlling data transfers, data from the host processor being written to the cache memory and subsequently destaged to the disks. The storage control unit continuously updates a variable indicating the number of written-to segments resident in the cache memory that have not been destaged to the disks. The variable is stored in the RAM. A File Status flipflop is responsive to the variable to produce a 'good file' signal when the variable is zero. The File Status flipflop is provided with an auxiliary power supply to maintain it in its present state in the event all power to the cache memory is terminated. Upon restoration of power after a complete power loss, the output of the status flipflop may be sampled by a command from the host processor to find out if any data was lost because written-to segments were present in the cache memory at the time all power was lost. The output of the File Status flipflop is also utilized to inhibit manually actuated functions which would destroy or invalidate written-to segments in the cache memory if the power to the cache memory were turned off, the cache memory were taken off line, or the port select switches between cache memory and the storage control unit were actuated to change port connections.

Cache/disk file status indicator with data protection feature

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Shoreview, MN, United States of America

Craig B Johnson