Texas Instruments Corporation

Craig B Greenberg

Kevin M Ovens

Roland Karl Son

Jay A Maxey, Jr

Indumini W Ranmuthu

Indumini Ramuthu

A system includes an output terminal and a linear switch circuit coupled to the output terminal. The linear switch circuit includes a first power field-effect transistor (FET) having: a first channel width; a control terminal; a first current terminal; and a second current terminal, wherein the second current terminal is coupled to the output terminal. The linear switch circuit also includes a second power FET having: a second channel width smaller than the first channel width; a control terminal; a first current terminal coupled to the first current terminal of the first power FET; and a second current terminal coupled to the output terminal. The system also comprises a control circuit coupled to the control terminal of the first power FET and to the control terminal of the second power FET. The control circuit detects a drain-to-source voltage (V) saturation condition and controls the first and second power FETs accordingly.

Linear switch circuits and methods

A semiconductor memory is disclosed having a primary memory array (12) and a dummy column (14) associated therewith that is comprised of a plurality of dummy memory cells (70). The dummy memory cells have a predetermined value stored therein and are sensed with a dummy sense amplifier (18). The dummy sense amplifier (18) has a predetermined offset disposed therein, such that it is in a predetermined state prior to the bit lines separating a sufficient amount to detect the logic state in the dummy memory cell, with an offset disposed therein. This offset prevents the state of the dummy sense amp from being changed until the bit lines are separated by a predetermined value. The primary sense amplifiers associated with the primary memory array (12) are not enabled until the dummy sense amplifier has detected the dummy bit lines as being separating by the predetermined amount. Once this bit line separation has been detected, the primary sense amplifiers are enabled, and the data stored in the accessed memory of the primary memory array (12) latched into the primary sense amplifiers.

Timing control for clocked sense amplifiers

A NOR decode circuit which includes a latch composed of a pair of n-channel transistors and a pair of p-channel transistors with the p-channel transistor of one latch portion coupled to a reference circuit transistor via a first pass transistor and the p-channel transistor of the other latch portion coupled to the address select line controlled transistors via a second pass transistor. The pass transistors are also controlled by an enable row (ENROW) signal. The address transistors are larger and conduct more current than the reference transistor. When ENROW is activated, the n-channel transistors of the latch are enabled and current passes through one side of the latch circuit and through a third transistor in parallel with the address transistors if any of the address transistors are turned on. Current also flows through the other side of the latch circuit and through a fourth transistor in parallel with the reference transistor. The second pass transistor conducts a current I.sub.1 plus the current through the reference transistor (I.sub.ref) and the first pass transistor conducts a current I.sub.1 plus the current through an address transistor (nI.sub.ref). Therefore, the second pass transistor conducts a current I.sub.1 +I.sub.ref and the first pass transistor conducts a current I.sub.1 +nI.sub.ref. The difference between these currents, i.e. (n-1)I.sub.ref, is amplified by the latch, causing the row line to remain low when an address transistor is selected and causing the row line to be high when none of the address transistors is selected.

Dynamic NOR decoder using current mode sensing techniques

The invention disclosed herein comprises a memory architecture using a new power saving ROW decode implementation. The new power saving ROW decode implementation uses a built in column mux of two. Two ROW drivers are provided for each ROW address. Each row signal from an individual ROW driver connects to every other memory cell (10). An individual ROW driver is selected based on the select signals used in the column mux. Being that the ROW drivers are muxed along with the columns, only memory cells of interest are selected. All unselected memory cell bit lines remain precharged from the previous precharge cycle thus reducing precharge power consumption as compared with previous memory architectures.

Memory architecture using new power saving row decode implementation

A flip-flop having a master section including two switching transistors is provided with output loading transistors to drive the two transistors into saturation in the event of a metastable condition causing input is present. By driving the switching transistors into saturation they become inactive and background noise cannot cause proprogation of the metastable condition to subsequent flip-flip stages.

Metastable tolerant latach

A flip-flop has a master section (74) comprising two transistors (40, 48). The second transistor (48) has two emitters, the second emitter conducting in response to a metastable condition wherein both transistors (40,48) are conducting concurrently, resulting in a metastable output. The second emitter (76) draws additional current through the second transistor (48) after a delay provided by a second clock (78), thus disrupting the equilibrium of the master section (74). By drawing additional current, the second transistor (48) will turn the first transistor (40) off, enabling a valid output.

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Rowlett, TX, United States of America

Craig B Greenberg