Ncr Corporation

Craig A Walrath

Gene F Young

Thomas F Heil

Edward A McDonald

Jimmy D Pike

Arthur F Cochcroft, Jr

Michael R Hilley

James M Ottinger

Daniel C Robbins

Randolph G Young

Bobby W Batchler

Terry S Strickland

Barry C Sudduth

James L Bradshaw

P Chris Raeuber

Marti D Miller

Jim D Pike

Jeff A Hawkey

An interleave lock arrangement for a computer system ensures the atomicity of a data transfer operation over a selected bus between a selected intelligent controller and a selected memory interleave, without interfering with data transfers over unselected buses between unselected intelligent controllers and unselected memory interleaves. An interleave lock signal issued by the selected intelligent controller over the selected bus is detected by and prevents only unselected intelligent controllers on the selected bus from executing bus cycles while the interleave lock signal is being asserted.

System for preventing an unselected controller from transferring data

A retry scheme for optimizing use of a first bus in a computer system which includes a plurality of bus masters connected through the first bus to an interface circuit and second bus. The interface circuit includes logic for generating a busy signal when the second bus is in a busy state and logic for generating a retry signal when the interface circuit is addressed by a bus master while the second bus is in a busy state. Each bus master includes logic for receiving the retry signal and relinquishing control of the common bus upon receipt of the retry signal from the interface circuit. A bus arbiter includes logic for receiving the busy signal and preventing any bus master seeking access to the second bus from participating in arbitration for control of the common first bus until the busy signal has been negated. Thus, during the term of the busy signal the first bus may be controlled by any bus master not requiring access to the shared resource. Upon negation of the busy signal, all bus masters will be permitted to compete for ownership of the bus.

Retry scheme for controlling transactions between two busses

A dual-port processor architecture wherein a first port interfaces to a PCI bus and a second port interfaces to a RAMBUS channel.

Multi-port processor with peripheral component interconnect port and

A method of transferring data words that include data bytes within a computer having a main memory, a processor and a cache memory, with the processor being able to cause data words to be transferred in a burst mode from the cache memory to the main memory in one of a plurality of predetermined sequences, includes the following steps: (1) determining which data words of a group of data words located in the cache memory include data bytes which have been modified, (2) selecting one sequence of data words of the plurality of predetermined sequences of data words which includes (a) all of the data words of the group of data words that include data bytes which have been modified, and (b) a minimum number of data words of the group of data words that include no data bytes which have been modified, and (3) causing the one sequence of data words selected in the selecting step to be transferred in the burst mode from the cache memory to the main memory.

Method and apparatus for transferring data within a computer using a

Multiple processor systems are configured to include at least two system or memory buses with at least two processors coupled to each of the system buses, and at least two I/O buses which are coupled to the system buses to provide multiple expansion slots hosting up to a corresponding number of I/O bus agents for the systems at the cost of a single system bus load for each I/O bus. Each of the system and I/O buses are independently arbitrated to define decoupled bus systems for the multiple processor systems of the present invention. Main memory for the systems is made up of at least two memory interleaves, each of which can be simultaneously accessed through the system buses. Each of the I/O buses are interfaced to the system buses by an I/O interface circuit which buffers data written to and read from the main memory or memory interleaves by I/O bus agents.

Architectures for computer systems having multiple processors, multiple

In a computer, when a block of data is written to memory, it is common to attach a control word to the data. The control word is placed at a pre-arranged location, generally separate from the data. The control word contains important information about the data, such as starting address, length, etc. The presence of the control word indicates that the data is valid. Sometimes, for various reasons, the control word is written before all the data is written. This premature availability of the control word gives false information: the data is not yet completely written, yet the presence of the control word indicates otherwise. The invention prevents such a problem by preventing premature writing of the control word.

Method and apparatus for storing a data block in multiple memory banks

Growing community of inventors

Easley, SC, United States of America

Craig A Walrath