Nxp B.v.

Zilog, Inc.

Signetics

North American Philips Corp., Signetics Div.

Craig A MacKenna

Neil Edward Birns

Gyle Dee Yearsley

Gregory Goodhue

Cecil H Kaplinsky

Ata Khan

Monte J Dalrymple

Zhimin Ding

Hanumanthrao Nimishakavi

Rob Cosaro

Pankaj Shrivastava

Ravi Swami

Rick Varney

Prithvi Nagaraj

Jan-Kwei J Li

A counter/timer circuit and a method of operating the counter/timer circuit are described. In one embodiment, a method of operating a counter/timer circuit involves determining a match condition by comparing a count value of the counter/timer circuit with a value stored in a match register of the counter/timer circuit and delaying an assertion of the match condition based on a value programmed in a match companion register of the counter/timer circuit. The match companion register is associated with the match register. Other embodiments are also described.

Timer match dithering

A counter/timer circuit and method of generating timed output signals using the counter/timer circuit, uses multiple counters that are configurable to operate as one or more counters. The counters are controlled by control signals from a control logic circuitry of the counter/timer circuit, where at least some of the control signals are dependent on event signals generated by an event generation module of the counter/timer circuit. The generated event signals are based on at least one of: an input signal, an output signal, and a counter match, qualified by a state value associated with the counters.

Universal counter/timer circuit

Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks.

Microcontroller with an interrupt structure having programmable priority levels with each priority level associated with a different register set

A microcontroller using an optimized buffer replacement strategy comprises a memory configured to store instructions, a processor configured to execute said program instructions, and a memory accelerator operatively coupled between the processor and the memory. The memory accelerator is configured to receive an information request and overwrite the buffer from which the prefetch was initiated with the requested information when the request is fulfilled by a previously initiated prefetch operation.

Memory accelerator buffer replacement method and system

Flash-type memory access and control is facilitated (e.g., as random-access memory). According to an example embodiment, an interface communicates with and controls a flash memory circuit over a peripheral interface bus. The interface uses a FIFO buffer coupled to receive data from and store data for the flash memory circuit and to provide access to the stored data. An interface controller communicates with the flash memory circuit via the peripheral interface bus to initialize the flash memory circuit and to access data thereto, in response to requests from a processor. In some applications, the flash memory circuit is initialized by sending commands to it. The interface may be placed into a read-only mode in which data in the flash memory is accessed as part of main (computer) processor memory, using the FIFO to buffer data from the flash.

Flash memory interface

A controller for executing instructions has one the order of five addressing modes and can allow executing of processes concurrently in multiple modes. A specific embodiment can effectively run legacy code written for the Z80 micoprocessor without requiring recompiling of code. An optional embodiment includes autonomous Multiply/Accumulator Engine (MAC) optimized to perform sum-of-products (SOP) operations with little controller overhead, making the invention capable of more effectively handling a number of processing tasks, particularly tasks related to digital signal processing (DSP).

Method and apparatus for an enhanced processor

An improved DMA controller is provided. The improved DMA controller uses a peripheral control bus which has scan codes to indicate the DMA channel, conventional data request/data acknowledge lines, and additional lines indicating a 'terminate,' 'type fetch,' 'end of buffer' and 'store status.' List entries are associated with the buffers in the memory. Each list entry has a type/status field which can be coded with information indicating 'ready buffer,' whether to notify 'end of buffer,' 'buffer in progress,' 'completed buffer without status,' 'completed buffer with status,' 'ready buffer with command,' and 'ready buffer without command.' The type of status byte can be checked before processing the buffers.

DMA with dynamically assigned channels, flexible block boundary

An ICE system for emulating a device includes an EPROM storing control code, at least one RAM storing user code and data, a processor alternatively executing the control code and user code, and memory map switch logic dynamically switching the memory address map of the processor between monitor and user state configurations so as to minimally impact the target environment by maximizing the available memory address space for the user code and data when the processor is executing the user code.

In-circuit emulation system with minimal impact on target environment

In an environment where a contact of a mother board is connected to a logic HIGH level voltage through a strong pull-up resistor, and a corresponding contact of an add-in board is connected to an open-drain driver, such that a control line driven by the open-drain driver is provided through the two contacts in normal mode operation when the two contacts make electrical connection, a circuit to sense whether or not the contact of the add-in board is making electrical connection with the contact of the mother board includes a weak pull-down resistor connected at one end to a node connecting the output of the open-drain driver to the contact of the add-in board, and connected at the other end to a ground reference. Accordingly, a voltage detected on the node is pulled up close to the logic HIGH level voltage if the contact of the add-in board is making electrical connection with the contact of the mother board and the open-drain driver is turned off, and is pulled down close to ground if the contact of the add-in board is not making electrical connection with the contact of the mother board and the open-drain driver is turned off. The voltage thus detected is provided to other circuitry on the add-in board, and/or back to a host computer on the mother board.

Circuit for sensing whether or not an add-in board is inserted into a

By monitoring various combinations of control signals generated by a microprocessor in a computer system in the first operational cycles after it is reset, a peripheral circuit sets itself to respond appropriately to control signals from the microprocessor according to any of several different protocols. For example, an instruction from the microprocessor to write to or read from the peripheral circuit is implemented over two control lines with one of several possible protocols. The circuit determines which protocol is being used each time the system is initialized and thereafter knows when a read or write operation is being performed. Another example is the different wait or acknowledge protocols that various microprocessors use. The peripheral circuit can thus be used with a variety of microprocessors without having to provide sets of pins dedicated to each signal protocol used by available microprocessors, and without the necessity to load a configuration register in the peripheral circuit by the microprocessor as part of the initialization process.

Technique for automatically adapting a peripheral integrated circuit for

A bidirectional interrupt technique and mechanism is described for handling programmable length interrupt messages between two devices, preferably both processors, through dual, programmably defined memory queues. The technique and mechanism automatically updates a read and write address counter, a queue count register, and an interrupt count register for each direction of the flow of interrupts.

Queued interrupt mechanism with supplementary command/status/message

An input/output (I/O) processor and data processing system in which the processor receives and services interrupt request signals from I/O controllers, which requests may be internally or externally coded, and supervises blockwise transfer of data between an external memory associated with a main processing unit and the I/O controllers. The I/O processor includes an internal memory for storing information pertinent to data transfer from each I/O channel including the address where channel programs, decision tables and data buffers are maintained in external memory. A sequencer executes a specialized instruction set which includes instructions that invoke an interpretation means enabling examination of status registers of the I/O controllers and/or data values therefrom and the branching of execution based thereon. The I/O processor and I/O controllers may be interconnected with a local external memory via a local bus which is selectively coupled with a system bus interconnecting the main processor unit and main external memory.

System having a host independent input/output processor for controlling

A circuit which expands monochrome character image patterns to color form for use in a raster scanned computer display system. Monochrome patterns are expanded from one bit per pixel to n bits per pixel. Foreground and background colors are programmable in a pattern generator which uses data from the expanded source patterns to select appropriate colors and characters for a destination pattern to be displayed. The expanded multicolor image is generated by hardware.

Growing community of inventors

Los Gatos, CA, United States of America

Craig A MacKenna