Gte Laboratories Incorporated

University of Massachusetts

Raytheon Company

Other

Verizon Laboratories Inc.

Craig A Armiento

Alkim Akyurtlu

Marvin J Tabasky

Thomas W Fitzgerald

Paul O Haugsjaa

Edward D Kingsley

Mark A Rothman

Chirravuri Jagannath

Jagannath Chirravuri

Oshadha K Ranasingha

Victor Cataldo

Yuri A Piro

Andrew M Luce

Chan-Long Shieh

Michael Cooperman

Boris S Elman

Harry F Lockwood

Margaret B Stern

Vincent J Barry

Mahdi Haghzadeh

Kyle M Homan

Alfred Joseph Negri

John Alvin Thompson

Paul Melman

James R Chow

Theodore J Conrad

John W Lovell

Peter E Norris

Emil S Koteles

William E Elias

A N Choudhury

Albert M Forcucci

Paul O Haugasjaa

Francisco C Prince

Christopher R Areias

Emily Lamport

Christopher N Kuncho

Alexander Z Senckowski

David Musoke

Christopher J Bett

Nathan C Brown

Guinevere M Strack

Cameron Hardie

A method is provided to form a security barrier of an electronic device under protection. The method includes depositing a transformable dielectric material layer on the electronic device under protection, and converting a target portion of the transformable dielectric material layer into at least one electrical circuit structure having at least one measurable electrical characteristic. The method further includes depositing a thermal stabilizing material layer onto the transformable dielectric material layer.

Scalable method for security barriers

An ink stabilizing composition includes a polymeric network including an acrylate polymer and a plurality of high aspect ratio particles each having an aspect ratio of about 2:1 to about 30:1 and an average particle diameter of about 0.5 to about 1.2 micrometers.

Temperature-stabilization of convertible functional inks by disruption of conduction paths

A position tracking system includes a member extending along a lengthwise axis. Multiple position tracking elements (such as conductive strips) are fabricated to be exposed on a surface of the member. The multiple position tracking elements form a sequence along the lengthwise axis and are spaced apart from each other. The position tracking system further includes a probe. The probe monitors for presences and absence of the position tracking elements disposed in the sequence as the member and corresponding sequence of position tracking elements moves with respect to the probe. Based on the detected presence and absence of position tracking elements, a monitor resource of the position tracking system monitors parameters such as: i) a position of the member along the axis, ii) a rate of movement of the member along the axis over time, iii) a direction of movement of the member along the axis, etc.

Electronic position sensing system, method, and apparatus

A chip-embedded printed circuit board includes a cavity in a printed circuit board, a chip in the cavity of the printed circuit board, and a thixotropic dielectric filler in a gap in the cavity to seal the chip in the printed circuit board.

Nanocomposite material for ultraviolet curable direct write semiconductor applications

Among other concepts, this disclosure describes a thermal/optical/electronic authentication system (covert or non-covert) for device/system implementations. The authentication system may be based on different design parameters such as i) materials composition, ii) thickness of material, iii) geometry of material, iv) external effects including use of an external DC bias and curing, etc. The authentication testbeds can be configured to include one or more inks. Using such methods as discussed herein, the authentication can be broadened to include near-IR (700-900 nm), short wave IR (1-2.6 mm), and UVA (300-400 nm) or any spectrum. Printed resistors are very difficult to duplicate without Ag-BST13 ink. If necessary, a printed resistor network on a respective substrate can be hidden using a layer of non-sintered Ag-BST13 (non-conductive).

Multi-level authentication using different materials

A fabrication system is operable to form a structure (such as on a substrate) using a combination of a first (electrically) non-conductive material and a second (electrically) non-conductive. In one embodiment, the structure defined by the first material and the second material defines a void (passageway) in the structure. In one embodiment, exposed surfaces of the first non-conductive material and the second non-conductive material define the void in the structure. Subsequent to creating the structure including the void, the fabrication system fills the void (such as via injection) with an electrically conductive material. After the injected electrically conductive material (such as metal epoxy or other suitable material) solidifies, the fabrication system removes the first non-conductive material (sacrificial material) from the structure. The remaining second material provides structural support for the electrically conductive material.

Fabrication of circuit elements using additive techniques

An apparatus includes a heat exchanger configured to transfer heat to a fluid and to absorb heat from the fluid as the fluid flows between a warm end and a cold end of a cryocooler. The heat exchanger includes at least one section having a substrate of at least one allotropic form of carbon and a layer of nanoparticles on or over the substrate. The heat exchanger could include multiple sections, and each section could include one of multiple substrates and one of multiple layers of nanoparticles. The heat exchanger can further include pores through the multiple sections of the heat exchanger, where the pores are configured to allow the fluid to flow through the heat exchanger and to contact the substrates and the layers of nanoparticles. The nanoparticles could include at least one lanthanide element or alloy, and the substrate could include carbon nanotubes or graphene.

Cryocooler containing additively-manufactured heat exchanger

A printed electrical connector design includes two flat patterned thermoplastic plates printed with mechanical registration features that align conductive traces on the two plates of the electrical connector. A top plate is printed with a plurality of raised pedestals and a plurality of metallic traces. A bottom plate is printed with a plurality of recessed channels and a corresponding plurality of metallic traces. The plurality of recessed channels of the bottom plate are configured to mate with the plurality of raised pedestals on the top plate. The pedestals and channels of the top and bottom plates, respectively, serve to align the metallic traces that comprise the electrical connector. The printed electrical connector design allows printed electrical/electronic circuits and/or devices to be manufactured and interfaced with other printed electrical/electronic circuits and/or devices.

Electrical connectors, circuit boards, and fabrication techniques

A novel ferroelectric ink comprising multiphase Barium Strontium Titanate (BST) in a polymer composite is described. The ink can be employed using direct-ink writing techniques to print high dielectric constant, low loss, and electrostatically-tunable dielectrics on substrates. The substrates can be flexible such as plastics or rigid, such as substrates comprising semiconductor materials or ceramics and the like. The dielectric ink is made by suspending pre-sintered nano/submicron-sized particles of BST in a thermoplastic polymer with a solvent. After printing with the ink, a low temperature curing process is performed at temperatures below 200&#xb0; C., a temperature too low to sinter BST. Fully printed devices, such as a varactor and a phase shifter using direct ink writing methodologies are described.

Ferroelectric nanocomposite based dielectric inks for reconfigurable RF and microwave applications

A method is provided for estimating a number of digital subscriber line nodes ( ) required to supply, from a line supply source ( ), a geographically distributed network of substantially sequentially numbered twisted pair lines with digital subscriber line service. The method comprises the steps of: storing, in number order, data entries for every twisted pair line of the network, each data entry comprising a pair number and a line length of the respective twisted pair line in relation to the line supply source ( ); sorting the entries stored in the database by line length; isolating those sorted entries whose twisted pair lines have a line length greater than a predetermined maximum line length in relation to the line supply source ( ); sorting the isolated entries by number; and discriminating, from the sorted isolated entries, the presence of discrete groupings of substantially contiguous entries.

Method and apparatus for calculating the number of very high speed digital subscriber line nodes

Provided herein are methods and systems for providing wide bandwidth using the present twisted pair telephone network. The methods and systems increase the bandwidth of ADSL by statistically sharing the bandwidth of many twisted pair in the neighborhood. An active subscriber would communicate over several twisted pair in the neighborhood, thereby obtaining a dramatic increase in bandwidth.

Broadband architecture using existing twisted pair

A heterostructure device includes a ridge-waveguide laser monolithically integrated with a ridge-waveguide rear facet monitor (RFM). An integral V-groove etched directly into the device substrate enables passive alignment of an optical fiber to the active region of the laser. The layer and RFM facets were formed using an in-situ multistep reactive ion etch process.

Method for forming a semiconductor device structure having a laser

A waferboard assembly incorporates mechanical registration features into a substrate platform to facilitate the passive alignment of lasers integrated on a chip to fibers in integral contact with the substrate. The waferboard includes two front pedestal structures and one side pedestal structure, and two vertical post structures within a mounting region defined by the pedestal struutures. The laser chip is mounted on the vertical post structures, and placed in concurrent abutting contact with the pedestal structures. The waferboard is fabricated by etching the substrate to form the front and side pedestal structures, and etching the substrate to define the grooves. In order to form the post structures, a polyimide material is deposited on the substrate using an appropriate mask.

Waferboard structure

A heterostructure device includes a ridge-waveguide laser monolithically integrated with a ridge-waveguide rear facet monitor (RFM). An integral V-groove etched directly into the device substrate enables passive alignment of an optical fiber to the active region of the laser. The laser and RFM facets were formed using an in-situ multistep reactive ion etch process.

Monolithically integrated semiconductor structure and method of

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Acton, MA, United States of America

Craig A Armiento