Intel Corporation

Cory Mason

Kemal Aygun

Dong-Ho Han

Stephen H Hall

Jun Liao

Konika Ganguly

Emile Davies-Venn

Stephen Christianson

M Reza Zamani

Kirankumar Kamisetty

Techniques for fabricating a package substrate and/or a stiffener for a semiconductor package are described. For one technique, a package substrate comprises: a routing layer comprising a dielectric layer. A stiffener may be above the routing layer and a conductive line may be on the routing layer, the conductive line comprising first and second portions, the first portion having a first width, the second portion having a second width, the conductive line extending from a first region of the routing layer to a second region of the routing layer, the first region being under the stiffener, the second region being outside the stiffener, the first portion being on the first region, and the second portion being on the second region. One or more portions of the conductive line can be perpendicular to an edge of the stiffener. The perpendicular portion(s) may comprise a transition between the first and second widths.

Stiffener and package substrate for a semiconductor package

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Hillsboro, OR, United States of America

Cory Mason