Intel Corporation

Google Inc.

Cory E Weber

Rishabh Mehandru

Stephen M Cea

Tahir Ghani

Aaron D Lilak

Anand S Murthy

Harold W Kennel

Seiyon Kim

Varun Mishra

Hemant V Deshpande

Jack T Kavalieros

Patrick R Morrow

Willy Rachmady

Mark Y Liu

Mark Armstrong

Daniel Bourne Aubertine

Sean T Ma

Patrick H Keys

Aaron A Budrevich

Ranjith Kumar

Abhishek A Sharma

Seung Hoon Sung

Szuya S Liao

Paul A Packan

Scott E Thompson

Michael G Haverty

Sadasivan Shankar

Gilbert W Dewey

Marko Radosavljevic

Van H Le

Justin K Brask

Glenn A Glass

Rafael Rios

Cheng-Ying Huang

Oleg Golonzka

Wilfred Gomes

Annalisa Cappellani

Shaofeng Yu

Martin D Giles

Sing-Chung Hu

Mark A Beiley

Pushkar Ranade

Zong-Fu Li

Kevin M Connolly

James E Breisch

Jung S Kang

Akira Kakizawa

Giuseppe Curello

Susmita Ghose

Sagar Suthram

Berni W Landau

Ajay K Sharma

Joseph W Parks, Jr

Ashutosh Ashutosh

Lucian Shifren

Christopher M Neumann

Max Wei

Steven M Cea

Benjamin Chu-Kung

Brian Joseph Greene

Gerhard Schrom

Sanaz Kabehie Gardner

Karthik Jambunathan

Dax M Crum

Justin R Weber

Ian R Post

Ritesh Jhaveri

Mohammad Hasan

Clifford L Ong

Dipanjan Basu

Sukru Yemenicioglu

Abhishek Anil Sharma

Leonard C Pipes

Patrick Theofanis

Mark Stettler

Pratik Patel

Sanaz Kabehie

Jiong Zhang

Wonil Chung

Tzu-Min Ou

Jack Yaung

Seahee Hwangbo

Memory arrays with backside components and angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as an 'angled transistor' if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. A component is referred to as a “backside component” if it is provided on the side of a semiconductor substrate that is opposite to the side over which the transistors of the memory arrays are provided. Memory arrays with backside components and angled transistors provide a promising way to increasing densities of memory cells on the limited real estate of semiconductor chips and/or decreasing adverse effects associated with continuous scaling of IC components.

Memory arrays with backside components and angled transistors

Gate-all-around integrated circuit structures having necked features, and methods of fabricating gate-all-around integrated circuit structures having necked features, are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires. Each nanowire of the vertical stack of horizontal nanowires has a channel portion with a first vertical thickness and has end portions with a second vertical thickness greater than the first vertical thickness. A gate stack is surrounding the channel portion of each nanowire of the vertical stack of horizontal nanowires.

Gate-all-around integrated circuit structures having necked feature

Embodiments of the present disclosure include integrated circuit structures having differentiated channel sizing, and methods of fabricating integrated circuit structures having differentiated channel sizing. In an example, a structure includes a memory region having a first vertical stack of horizontal nanowires having a first number of nanowires. The integrated circuit structure also includes a logic region having a second vertical stack of horizontal nanowires spaced apart from the first vertical stack of horizontal nanowires. The second vertical stack of horizontal nanowires has a second number of nanowires less than the first number of nanowires.

Integrated circuit structures having differentiated channel sizing

Structures having ultra-high conductivity global routing are described. In an example, an integrated circuit structure includes a device layer having a plurality of transistors. A plurality of metallization layers is above the plurality of transistors of the device layer. One or more of the metal layers includes a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin.

Integrated circuit structures having ultra-high conductivity global routing

Disclosed herein are source/drain regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a channel region including a semiconductor material; and a source/drain region at a side face of the channel region, wherein the source/drain region includes a semiconductor portion and a contact metal, and the semiconductor portion is between the contact metal and the semiconductor material.

Source/drain regions in integrated circuit structures

Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices

Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.

Gate-all-around integrated circuit structures having insulator fin on insulator substrate

Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

Forksheet transistors with dielectric or conductive spine

Fin doping, and integrated circuit structures resulting therefrom, are described. In an example, an integrated circuit structure includes a semiconductor fin. A lower portion of the semiconductor fin includes a region having both N-type dopants and P-type dopants with a net excess of the P-type dopants of at least 2E18 atoms/cm. A gate stack is over and conformal with an upper portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

Fin doping and integrated circuit structures resulting therefrom

Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling ('BTBT') effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.

Reducing off-state leakage in semiconductor devices

Embodiments of the present disclosure are based on extending a nanocomb transistor architecture to implement gate all around, meaning that a gate enclosure of at least a gate dielectric material, or both a gate dielectric material and a gate electrode material, is provided on all sides of each nanoribbon of a vertical stack of lateral nanoribbons of a nanocomb transistor arrangement. In particular, extension of a nanocomb transistor architecture to implement gate all around, proposed herein, involves use of two dielectric wall materials which are etch-selective with respect to one another, instead of using only a single dielectric wall material used to implement conventional nanocomb transistor arrangements. Nanocomb-based transistor arrangements implementing gate all around as described herein may provide improvements in terms of the short-channel effects of conventional nanocomb transistor arrangements.

Extension of nanocomb transistor arrangements to implement gate all around

Semiconductor nanowire devices having (111)-plane channel sidewalls and methods of fabricating semiconductor nanowire devices having (111)-plane channel sidewalls are described. For example, an integrated circuit structure includes a first semiconductor device including a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising a discrete channel region having <111> lateral sidewalls along a <110> carrier transport direction. The integrated circuit structure also includes a second semiconductor device including a semiconductor fin disposed above the substrate, the semiconductor fin having a channel region with a top and side surfaces, the channel region having <111> lateral sidewalls along a <110> carrier transport direction.

Semiconductor nanowire device having (111)-plane channel sidewalls

Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a gate electrode above the substrate, and a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer. The transistor further includes a contact electrode above the channel layer and in contact with a contact area of the channel layer. The contact area has a thickness determined based on a Schottky barrier height of a Schottky barrier formed at an interface between the contact electrode and the contact area, a doping concentration of the contact area, and a contact resistance at the interface between the contact electrode and the contact area. Other embodiments may be described and/or claimed.

Channel structures for thin-film transistors

Gate-all-around integrated circuit structures having insulator FIN on insulator substrate

Growing community of inventors

Hillsboro, OR, United States of America

Cory E Weber