Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies General IP Pte, Ltd.

Cory D Groth

Jeffrey R Rearick

Richard S Rodgers

An apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) includes operating a clock associated with the IC at a frequency (f) at which IC operation is sought to be determined, measuring the actual clock period (T) at a clock output, scan testing the IC, measuring the actual clock period (T) at the clock output, determining a delay by calculating the difference between Tand T, and compensating for the delay by increasing the clock frequency during scan test.

Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC)

An apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) includes operating a clock associated with the IC at a frequency (fTARGET) at which IC operation is sought to be determined, measuring the actual clock period (TCLOCK_OUT) at a clock output, scan testing the IC, measuring the actual clock period (TSCAN_CLOCK_OUT) at the clock output, determining a delay by calculating the difference between TSCAN_CLOCK_OUT and TOLOCK_OUT, and compensating for the delay by increasing the clock frequency during scan test.

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Cory D Groth