Mosaic Systems, Inc.

Environmental Research Institute of Michigan

Cornelius C Perkins

Herbert Stopper

A signal line network on a substrate for interconnecting IC chips is programmable after manufacture to define the desired connections. The signal lines comprise line segments arranged end-to-end in both horizontal and vertical directions and are connectible at their ends and the vertical and horizontal segments are connectible at their crossings. A dedicated contact pad is connected to each segment. A plurality of bonding pads are adjacent several segments and each pad has arms extending across the several segments and are individually connectible to them. All connectible junctions comprise amorphous silicon antifuses which are normally insulators and are selectively programmable after the substrate is manufactured by applying a voltage pulse across the antifuse to render it conductive. The pads are arranged in a pattern in cells, all cells having the same pad pattern to facilitate probe connections for programming and testing.

Programmable silicon circuit board

Disclosed is a wafer scale device 10, 201 on which is formed a layer of thin film as an interconnection system 203 with contact sites 202, 207 between the interconnection system 203 and die bonding sites 202 of the wafer 10, 201 to form a monolithic wafer. The interconnection system 203 has bonding sites on the surface of the wafer 10, 201 to which chips 11 are bonded to form a hybrid monolithic wafer system. The wafer 10 is packaged within a wafer package, FIG. 4, and the packaging system utilizes a header 20 which is a flexible circuit connector between the wafer package and first level circuit board 30.

Wafer scale package system and header and method of manufacture thereof

Disclosed is a wafer substrate for integrated circuits 1 which by itself may be made either of conductive or non-conductive material. This substrate carries two planes or layers of patterned metal 19,20, thus providing two principal levels of interconnection. A programmable amorphous silicon insulation layer 21 is placed between the metal layers. There are sheet lower metal layers with an insulator which permit power distribution across the wafer. Connections between the metal layers or between the metal layer and the substrate can be made through via holes in the insulator layers or layers, respectively. Pedestals are provided for bonding.

Growing community of inventors

Birmingham, MI, United States of America

Cornelius C Perkins