U.S. Philips Corporation

Koninklijke Philips Corporation N.v.

Cornelis Niessen

Cornelis Hermanus Van Berkel

Roelof H Salters

Ronald W Saeijs

Jozef L Van Meerbergen

Cornelis Am Mulder

Antoine Delaruelle

Marinus T Segers

Leendert Nederlof

Leonardus Hendricus Maria Sevat

Rene M Wijnhoven

Krijn Kuiper

Owen P McArdle

The invention relates to a device for parallel processing data and to a camera system comprising such a device. The camera system () comprises a sensor matrix (), a data converter (), a DSP (), a central controller (), a data buffer () and a processor matrix () consisting of processors (). The sensor matrix () converts incident electromagnetic radiation into pixel signals. The data converter () converts the pixel signals into data. The arrows () and () diagrammatically indicate the transport of pixel signals and data. The data buffer () is physically divided into a part (A) and a part (B) and functionally divided into an I/O register () and a memory bank (). The central controller () co-ordinates the different tasks. The processors () and the data buffer () have data ports () and further data ports () with inputs and outputs which are mutually connected in an electrically conducting manner using the connections (). The processors () are arranged in rows () which are mutually staggered, and columns (). This makes all connections () substantially straight. Due to the amount of connections, this reduces the surface area.

Device for parallel data processing, and camera system comprising such a device

Digital data processing electronic circuitry based on self-timed elements. The operating speed of the electronic circuitry is determined by its power supply voltage. Moreover, a buffer is connected either to the input or to the output of the electronic circuitry. A filling degree signal from the buffer is fed back to a control input of a power supply voltage controller for the electronic circuitry. In this way the supply voltage of the electronic circuitry is adjusted to control the data flow in such a way that the buffer tends not to fill up or to become empty.

Digital data processing circuit with control of data flow by control of

A buffer memory device comprising memory locations for successively storing successive groups of data units, the successive groups being presented during successive phases, the data units in each group having different buffer periods which are recurrent for all groups. A modulo address generator generates, for each group of data units, a series of addresses for selected locations in a memory wherein the data units will be stored, there being logic address intervals between the successive addresses in the relevant series which correspond to the buffer periods of the respective data units. In every two successive series the memory addresses are shifted by one address interval unit with respect to each other. An efficient data occupation of the memory can thus be realized with simple addressing, since the write addresses during any phase can be used as the read addresses for already stored data units. The buffer device can be used as an interleaver or de interleaver for error correction in CD apparatus.

Data buffer for the duration of cyclically recurrent buffer periods

A silicon-compilation method, a silicon-compiler arrangement, an abstract-circuit synthesis module usable in such arrangement, a machine-generated abstract circuit produced by such module, an electronic circuit generated by such method and a reset-free circuit produced by such arrangement. There are described a method and arrangement for silicon compilation. First, an algorithmic procedure to be executed by the electronic circuit is expressed in an imperative concurrent language. This, under execution of lexical, syntactic and semantic analysis is converted to a structure tree as an abstract representation of said procedure. This structure tree then is converted into an abstract circuit, wherein each basic component is a program module and each abstract channel corresponds to a program channel. Thereafter, the abstract circuit is converted into a concrete circuit, while obeying timing-organization constraints, circuitry-type constraints and technology constraints. Finally, the concrete circuit is converted into a very large-scale integrated-circuit layout.

Silicon-compiler method and arrangement

A device for processing digital signals includes combinatorial and sequential logic elements. For the testing of the device, a shift register can be formed from the sequential elements. A test pattern is applied thereto. The result of the processing of the test pattern is applied to the shift register. The output of the shift register is connected to a second shift register which forms a moving multibit sum pattern from a received series of result patterns by way of a feedback circuit to at least one Exclusive-OR-element. An output of the feedback circuit is connected to an input of the first shift register in order to apply a subsequent test pattern thereto. After completion of the test, the sum pattern formed is checked.

Device for testing a circuit comprising sequential and combinatorial

An integrated circuit in dynamic MOS logic is composed of combinatory and sequential logic elements. Each of the latter comprises a succession of an input gate, an intermediate gate and an output gate which are activated to conduct by a corresponding phase of the first one and subsequent phases of a clock pulse cycle. The combinatory logic elements are all composed of gates of a single type, while the input signals are applied via the sequential logic elements and the output signals are output again via the latter elements. Thus, in the combinatory network only a sole type of interference is still relevant.

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Eindhoven, Netherlands

Cornelis Niessen