U.S. Philips Corporation

Cornelis Am Mulder

Henricus E Wulms

Arie Slob

Roelof H Salters

Cornelis Gerardus Visser

Cornelis Niessen

Albert Schmitz

Godefridus H Heijnen

Leendert Nederlof

Rene M Wijnhoven

Ernest O Van Der Stelt

Willibrordus H Van De Spijker

The electric lamp has a quartz glass lamp vessel in which a light source is accommodated. The lamp vessel is covered by an interference film which has layers of alternatingly silica and a material of relatively high refractive index. A silica containing adhesive layer is in between the lamp vessel and the film. The adhesive layer has a content of boron oxide and/or phosphorus oxide.

Electric lamp with adhesion layer and interference layer

The colored electric lamp has a lamp vessel (1) carrying a colored translucent interference filter (12) of alternately SiO.sub.2 layers and layers of comparatively high refractive index. In the filter, layers of high refractive index have an optical thickness smaller than 1/4.lambda..sub.0, while SiO.sub.2 layers have an optical thickness larger than 1/4.lambda..sub.0. An SiO.sub.2 layer of 500-900 nm thickness can be present on the filter. The light emitted by the lamp has a higher color saturation and the filter has a better adherence to the lamp vessel than in the case of a lamp comprising a conventional filter having an equal overall thickness of layers of high refractive index.

Filter for colored electric lamp

A high speed I.sup.2 L circuit having a topology which is based on a layout of parallel arranged gate circuits in which the inverter transistors of each gate circuit are arranged in a row and below the signal lines to which they are connected, said signal lies extending transversely to the rows, while the complementary transistors for the current supply of the inputs of the gate circuits are situated laterally beside the signal lines. Said layout facilitates the designing of comparatively compact I.sup.2 L circuits in which various measures to increase their speed can be taken, for example, the use of dielectric isolation, reduction of the input series resistance, reversal of the doping profile and the application of a potential difference between the bases of the complementary transistors and the common emitter of the inverter transistors.

Integrated circuit

An integrated circuit in dynamic MOS logic is composed of combinatory and sequential logic elements. Each of the latter comprises a succession of an input gate, an intermediate gate and an output gate which are activated to conduct by a corresponding phase of the first one and subsequent phases of a clock pulse cycle. The combinatory logic elements are all composed of gates of a single type, while the input signals are applied via the sequential logic elements and the output signals are output again via the latter elements. Thus, in the combinatory network only a sole type of interference is still relevant.

Dynamic MOS-logic integrated circuit comprising a separate arrangement

A logic circuit in I.sup.2 L wherein across the base-emitter paths of the NPN-transistors diodes are connected in order to reduce the propagation delay time of the logic circuit.

Logic circuit

A method of making a semiconductor device is described in which opposite-type impurities are introduced into the same surface of a substrate in such manner that the region of impurities of the opposite-type to that of the substrate overlaps completely the other substrate surface region. Then an epitaxial layer is grown on the surface of the substrate. There is thus formed two buried layers of which the one with the same type conductivity of the substrate is completely separated and isolated from the latter by the buried layer of opposite-type conductivity. Methods are also described for the manufacture of complementary bipolar transistors, in which the pnp type is made by the above described method.

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Eindhoven, Netherlands

Cornelis Am Mulder