Taiwan Semiconductor Manufacturing Comp. Ltd.

Mosaid Technologies Corporation

U.S. Philips Corporation

Advanced Memory International, Inc.

Accelerix Limited

Other

Sige Semiconductor, Inc.

Cormac Michael O'Connell

Atul Katoch

Shih-Lien Linus Lu

Peter B Gillingham

Randy R Torrance

Sanjeev Kumar Jain

Peter H Voss

David E Jones

Dennis A Fielder

James H Derbyshire

Brent Keeth

David V James

Bruce Millar

Saman M I Adham

Kun-Hsi Li

Troy A Manning

Terry R Lee

Kevin J Ryan

Yoshikazu Morooka

Stephen Joseph Kovacic

Henry Stracovsky

Cathal G Phelan

Desi Rhoden

Donald N North

Hans Ontrop

Thomas J Davies

Mayank Tayal

Leonardus C Pfennings, Deceased

Richard Foss

Hans A Wiggers

Henricus J Kunnen, Legal Representative

Arun Achyuthan

David B Gustavson

Randall R Torrance

Philip S Shaer

Jean Crepeau

Systems and method are provided for operating a multi-array memory that includes a left memory array and a right memory array of a memory bank. A command is received at memory input pins. A signal representative of the command is propagated to an array control inhibitor. An array inhibit command is received on one or more other pins of the memory and provided to the array control inhibitor. The array control inhibitor is used to prevent arrival of the command to one of the left memory array and the right memory array based on the array inhibit command.

Memory circuit including an array control inhibitor

Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator comprising: a plurality of PUF cells, wherein each of the plurality of PUF cells comprises a first MOS transistor and a second MOS transistor, wherein terminal S of the first MOS transistor is connected to terminal D of the second MOS transistor at a dynamic node, terminal D of the first MOS transistor is coupled to a first bus and terminal G of the first NMOS transistor is coupled to a second bus, and terminals S and G of the second NMOS transistor are coupled to ground; a plurality of dynamic flip-flop (DFF) circuits wherein each of the plurality of DFF circuits is coupled to each of the plurality of PUF cells respectively; a population count circuit coupled to the plurality of DFF circuits; and an evaluation logic circuit having an input coupled to the population count circuit and an output coupled to the plurality of DFF circuits.

Method for PUF generation using variations in transistor threshold voltage and subthreshold leakage current

Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array that comprises a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two pre-charge transistors, at least one enable transistor, and at least two storage nodes, wherein the at least two storage nodes are pre-charged with substantially the same voltages by the respective at least two pre-charge transistors allowing each of the plurality of bit cells having a first metastable logical state; and an authentication circuit, coupled to the PUF cell array, wherein the authentication circuit is configured to access and determine second logical states of bit cells in at least one row of the PUF cell array by turning on the at least one enable transistor and turning off the at least two pre-charge transistors of each of the bit cell in the at least one row of the PUF cell array, and based on the determined second logical states of the bit cell in the at least one row of the PUF cell array, to generate a PUF signature.

PUF generators based on SRAM bit cells

Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, wherein each of the plurality of columns is coupled to at least two pre-discharge transistors, and each of the plurality of bit cells comprises at least one enable transistor, at least two access transistors, and at least two storage nodes, and a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to pre-charge the at least two storage nodes with substantially the same voltages allowing each of the plurality of bit cell having a first metastable logical state; to determine a second logical state; and based on the determined second logical states of the plurality of bit cells, to generate a PUF signature.

Method and apparatus for logic cell-based PUF generators

An Orthogonal Dual Port Ram (ORAM) memory cell may be provided. The ORAM memory cell may comprise a data storage element, a first port bit line, and a second port bit line that may be substantially perpendicular to first port bit line. The ORAM memory cell may further comprise a first word line that may be substantially perpendicular to first port bit line wherein the ORAM memory cell may be configured to read data from the data storage element to the first port bit line when the first word line is enabled. The ORAM memory cell may further comprise a second word line being substantially perpendicular to the second port bit line wherein the ORAM memory cell may be configured to read data from the data storage element to the second port bit line when the second word line is enabled.

Orthogonal dual port RAM (ORAM)

A method for utilizing a plurality of physical unclonable function (PUF) cells to generate a signature key with a desired bit length is provided. The method includes setting a state of each of the plurality of PUF cells to a uniform level; obtaining an order of change in the state of at least a portion of the plurality of PUF cells; and generating the signature key at least based on the order.

System to generate a signature key and method of operating the same

Orthogonal dual port ram (ORAM)

A physically unclonable function (PUF) device and a method for maximizing existing process variation for a physically unclonable device are provided. The method of maximizing process variation of the PUF device includes: modeling a physically unclonable function (PUF) device, comprising a plurality of PUF cells, selecting the size of transistors in the PUF device to be smaller than a predetermined size defined according to a design rule check (DRC) and generate maximum variations among the plurality of PUF cells, varying the material of the PUF device, and driving the PUF device with a predetermined voltage. The physically unclonable device includes: a plurality of PUF cells, configured to generate an output. Each of the plurality of PUF cells includes a harvester circuit, configured to generate a bit line and a complementary bit line. The harvester circuit is selected to be smaller than a predetermined size defined according to a design rule check (DRC) and generate maximum variations among the plurality of PUF cells; and a sense amplifier having a plurality of transistors configured to receive a first input signal and a second input signal from the harvester circuit.

Physical unclonable device and method of maximizing existing process variation for a physically unclonable device

Growing community of inventors

Kanata, Canada

Cormac Michael O'Connell