Imp Inc.

International Microelectronic Products

Minnesota Mining and Manufacturing Company

Corey D Petersen

Douglas L Hiser

Jaime E Kardontchik

Moiz Khambaty

Hans W Klein

Jamie E Kardontchik

Paul S Cheung

A method of threshold adjust implantation which involves the implanting of some of the PMOS FETs' channels on a CMOS circuit so the PMOS FETs have a threshold voltage of substantially zero volts, the implanting involves an additional implantation of ions into the PMOS FET' channels in addition to the implantation required to raise the PMOS FET' threshold voltage from the native threshold voltage to the normal threshold voltage.

CMOS process and circuit including zero threshold transistors

An integrated circuit adapted for use in a data path of a disk storage system of a type wherein data is recorded at different rates depending upon the storage track of the data and includes servo bursts of head positioning signals disbursed throughout the data on all of the tracks. The circuit includes a variable cut off low pass filter that is adjusted both for the rate of data being read and for the rate of the servo bursts when being read. An automatic gain control and a pulse detector are similarly dynamically adjusted in characteristics to fit that of the data and servo bursts when each is being read from the disk. An output of the filter provides both read data and head positioning signals. A write data path is also provided as part of the circuit.

Computer disk drive integrated data path circuit optimized for handling

A digitally programmable Bessel filter includes a plurality of serially connected stages or biquads with each biquad including a plurality of programmable operational transconductance amplifiers. The first stage of the filter provides an all pass equal amplitude response. Two stages provide pulse slimming (first and second derivatives of an input pulse), and three stages provides a sixth order Bessel low pass function. The operational transconductance amplifiers are controlled by a fine tuning control signal, and an array of integrating capacitors are selectively controlled by a coarse tuning signal. The fine tuning and coarse tuning signals are generated in a phase locked loop from a reference clock and a reference biquad which receives the reference clock.

Programmable operation transconductance amplifier

A single integrated circuit chip provides an interface to both magneto-resistive read elements and inductive write elements of a plurality of read/write heads of a disk drive mass data storage system. Separate multiplexers and current sources are used for the read and write channels. The read element of a head selected by one of the multiplexers is preamplified on the chip. A write driver circuit is also provided, being connected to a write element of a head selected by the other of the multiplexers.

Disk drive interface combining a magneto-resistive read and inductive

A method of threshold adjust implantation which involves the implanting of some of the PMOS FETs' channels on a CMOS circuit so the PMOS FETs have a threshold voltage of substantially zero volts, the implanting involves an additional implantation of ions into the PMOS FETs' channels in addition to the implantation required to raise the PMOS FETs' threshold voltage from the native threshold voltage to the normal threshold voltage.

A digitally programmable Bessel filter includes a plurality of serially connected stages or biquads with each biquad including a plurality of programmable operational transconductance amplifiers. The first stage of the filter provides an all pass equal amplitude response. Two stages provide pulse slimming (first and second derivatives of an input pulse), and three stages provides a sixth order Bessel low pass function. The operational transconductance amplifiers are controlled by a fine tuning control signal, and an array of integrating capacitors are selectively controlled by a coarse tuning signal. The fine tuning and coarse tuning signals are generated in a phase locked loop from a reference clock and a reference biquad which receives the reference clock. The phase locked loop includes a phase detector responsive to the reference clock and the reference biquad, whose output is integrated.

Digitally programmable linear phase filter having phase equalization

A constant loop gain phase lock loop for recovering a clock from non-uniformly spaced data pulses utilizes a programmable current source and charge pump whereby the current into the charge pump is proportional to the number of VCO clock periods between data pulses. As the time between pulses increases the current charging the pump increases and when the time between pulses decreases the current charging the pump decreases to maintain a constant loop gain independent of the data pattern.

Phase locked loop having constant gain for recovering clock from

A preamplifer for use with a magneto-resistive playback head in which a d.c. current source provides current through a field effect transistor and the magneto-resistive element to ground. An operational transconductance amplifier included in a feedback loop provides a bias voltage for the field-effect transistor, whereby the voltage across the said magneto-resistive element is held constant while the resistance of said element changes. The resulting a.c. current flowing through the magneto-resistive element flows only through the feedback loop and an output resistor connected across the inputs of the operational transconductance amplifier. The amplification of the circuit is approximately the resistance of the output resistor divided by the resistance of the magneto-resistive element.

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Pleasanton, CA, United States of America

Corey D Petersen