Freescale Semiconductor,inc.

Nxp Usa, Inc.

Cor Voorwinden

Michael Priel

Ludovic Oddoart

Gordon P Lee

Nadim Khlat

Christopher K Chun

Dan Kuzmin

David Michael Schlueter

Olivier Tico

Christopher K Y Chun

Dennis Joe Cashen

Berengere Le Men

Vincent Teil

Philippe Debosque

Alexandre Crisnaire

Michel Priel

P Lee Gordon

A method for media access control, the method includes generating at least one media access grant in response to at least one media access request. The method further includes monitoring a data line, while maintaining at least a clock line in a low power mode, to detect at least one media access request generated by at least one component connected to the data line and to the clock line; and forcing the at least clock line to exit the low power mode and starting a contention prevention period, when the media access controller or at least one component requests to access the data line. Also disclosed is a device for implementing the method of media access control.

Device and method for media access control

A battery charging circuit comprises: a first voltage regulator, wherein the first voltage regulator has a control input designed for reception of a signal generated by a current metering circuit; the current metering circuit; and a terminal for connecting a battery. An electronic device, in particular a mobile device, comprises a battery charging circuit as defined above.

Battery charging circuit and electronic device

A voltage supply circuitry is capable of coupling to wired audio headset circuitry and configurable to operate in a first mode, wherein the voltage supply circuitry provides a voltage supply to the wired audio headset functionality circuitry. The voltage supply circuitry is further capable of coupling to visual indication circuitry and further configurable to operate in a second mode, wherein the voltage supply circuitry provides a voltage supply to the visual indication circuitry.

Voltage supply circuitry and integrated circuit therefor

A secure real time clock (RTC) system is provided, comprising a secure RTC, a frequency signal generator, and a frequency adjuster connected between the secure RTC and the frequency signal generator to receive a signal having a first frequency from the frequency signal generator. On receipt of a first control signal the frequency adjuster outputs the signal having the first frequency to the secure RTC, and on receipt of a second control signal the frequency adjuster adjusts the signal having the first frequency to generate a signal having a second frequency, the second frequency being lower than the first frequency, and outputs the signal having the second frequency to the secure RTC. A clock line transmits the signal having the first frequency and the signal having the second frequency from the frequency adjuster to the secure RTC, and has a first power consumption when transmitting the signal having the first frequency and a second power consumption when transmitting the signal having the second frequency, the first power consumption being greater than the second power consumption.

System and method for secure real time clocks

A power supply controller for a plurality of lighting components in a battery-powered apparatus. The power supply controller comprises a current source common to the lighting components, and a sequencer for coupling the current source sequentially to each of the lighting components with a repetition rate substantially faster than the flicker perception rate. Each of the lighting components comprises a respective array of lighting elements connected in series to receive the same current as the other lighting elements of the same lighting component.

Power supply controller for multiple lighting components

A device that has failure recovery capabilities and a method for power recovery. The method includes: detecting a potential power failure in response to a decrement rate of a supply voltage, and applying at least one failure recovery measure in response to a detected potential power failure. The device includes: a power source, an energy reservoir, at least one component, and a power failure circuit, adapted to detect a potential power failure in response to a decrement rate of a supply voltage.

Device having failure recovery capabilities and a method for failure recovery

A device and a method for frame synchronization, the method includes providing a high frequency clock signal over a clock line during a transmission of information over a data line connected to a media access controller and to at least one component; defining a short synchronization period; processing at least one signal conveyed over the data line during the short synchronization period to determine a presence of a synchronization error; and maintaining at least the clock line in a low power mode when the data line is substantially idle.

Method and device for frame synchronization

A switch controller has a charge pump, a selector switch connected to the charge pump, and a pre-charge power supply input connectable to the input of the selector switch. For each of the output channels being controlled, a power control switch is connected to an output of the selector switch. In response to commands, output channels are enabled and disabled, causing corresponding actions in the power control switches. When an output channel is to be activated, the output channel is selected by the selector switch and the pre-charge power supply connected to the input of the selector switch. The charging is completed by the charge pump and the enabled status of the power control switch is maintained by the charge pump.

Charge pump and control scheme

A method of converting a plurality of input signals on first and second converters, such that the first and second converters are both used when the plurality of signals comprises two signals, characterised in that said method comprises:

Method and apparatus for converting signals

A Universal Serial Bus transmitter comprising a USBTXP input and a USBTXM input for receiving respective data signals, and a USBP driver and a USBM driver for applying the respective data signals to USBP and USBM wires respectively. The transmitter comprises a transmit signal generator responsive to an asserting edge of a signal at one of the USBP and USBM inputs to define a leading edge of a transmit signal (USBTXIP) and to a corresponding de-asserting edge of a signal at the other of the USBP and USBM inputs to define the subsequent trailing edge of said transmit signal (USBTXIP). Even if the duty cycles of the input signals USBTXP and USBTXM are substantially different from 50%, this does not cause unacceptable jitter of successive crossover points nor cause the crossover point voltage level to be outside the USB tolerance, centred on 50% of the voltage swings of the USBP and USBM signals.

Universal serial bus transmitter

Power supply apparatus, especially for the active circuits of a portable radio communication device. The power supply supplies a direct voltage to a load that is connected to a first terminal, is comprising a rechargeable battery for connection to a second terminal, and a voltage generator for recharging the battery and supplying power to the load. The power supply includes first control means for controlledly supplying current from the voltage generator to the first terminal so as to control supply of current from the voltage generator to the load and for preventing reverse flow of current from the first terminal to the voltage generator, and second control means for controlledly supplying current between the first and second terminals so as to control supply of current from the voltage generator through the first control means to the battery and from the battery to the load.

Controlling power supply between a voltage generator, a load and a rechargeable battery

A terminal includes at least one wireless communication application module () and a plurality of further application modules (). Multiple radio frequency clock signals are generated for the different modules having respective clock frequency characteristics and including at least first and second clock frequencies that are not integral multiples nor sub-multiples of each other nor of a third frequency. The clock generation comprises reference frequency means (), fractional-N phase-locked loop frequency synthesizer means () responsive to the reference frequency means, and different automatic frequency control means for adjusting clock frequencies relative to received signals. The reference frequency means () is arranged to supply a common reference frequency signal to a plurality of the fractional-N phase-locked loop frequency synthesizer means () that supply the first and second clock frequencies respectively for the application modules. Selective activation means () selectively activates and de-activates the phase lock loop means as required by the corresponding application module or modules.

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Toulouse, France

Cor Voorwinden