Apple Inc.

Constantin Pistol

Daniel Allen Chimene

John Gregory Dorsey

Russell Alexader Blaine

Bryan R Hinch

Jeremy C Andrus

Andrei Dorofeev

Aditya Venkataraman

Cyril De La Cropte De Chanterac

James Michael Magee

Nigel R Gamble

James S Ismail

Ian D Kountanis

Matthias Knoth

Kushal Dalmia

James Robert Howard Hakewill

Dmitriy B Solomonov

Jaidev P Patwardhan

Matthew C Widmann

Shekhar S Srikantaiah

Prakhar Malhotra

An apparatus includes a processor circuit that includes a memory circuit, one or more processor cores, and a debug circuit. The debug circuit may be configured, in response to activation of a trace mode to record information indicative of instructions executing on the one or more processor cores, to write a trace data stream to the memory circuit that includes trace data collected on the instructions executing on the one or more processor cores. In response to a particular instruction within one of the processor cores specifying a write of a data value to an architecturally visible trace register, the debug circuit may be further configured to output the data value to the trace data stream as part of executing the particular instruction.

Hardware support for software event collection

Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

Scheduler for amp architecture with closed loop performance and thermal controller

Scheduling of work interval objects in an AMP architecture using a closed loop performance controller

Scheduler for amp architecture using a closed loop performance and thermal controller

A processing system can include a plurality of processing clusters. Each processing cluster can include a plurality of processor cores and a last level cache. Each processor core can include one or more dedicated caches and a plurality of counters. The plurality of counters may be configured to count different types of cache fills. The plurality of counters may be configured to count different types of cache fills, including at least one counter configured to count total cache fills and at least one counter configured to count off-cluster cache fills. Off-cluster cache fills can include at least one of cross-cluster cache fills and cache fills from system memory. The processing system can further include one or more controllers configured to control performance of one or more of the clusters, the processor cores, the fabric, and the memory responsive to cache fill metrics derived from the plurality of counters.

Performance telemetry aided processing scheme

Scheduler for AMP architecture with closed loop performance controller using static and dynamic thread grouping

Systems, apparatuses, and methods for instruction next fetch prediction. A scan-on-fill target predictor in a processor generates a predicted next fetch address for the instruction fetch unit. When a group of instructions is used to fill an instruction cache but is not currently being retrieved from the instruction cache for processing by other pipeline stages, the group of instructions are scanned to identify exit points of basic blocks within the group. An entry of a table in the scan-on-fill target predictor is allocated for an instruction in a basic block in the group when the basic block has an exit point with a target address that can be resolved within a single clock cycle. The scan-on-fill target predictor may perform a lookup of the table with the current fetch address. The prediction may be compared to a main branch predictor at a later pipeline stage for training purposes.

Scan-on-fill next fetch target prediction

Scheduler for amp architecture using a closed loop performance controller and deferred inter-processor interrupts

Systems, apparatuses, and methods for efficient program flow prediction. After receiving a current fetch address, a first predictor performs a lookup of a first table. When the lookup results in a miss and the first table has no available entries, the first predictor overwrites a given entry of the first table with the received fetch address, in response to detecting a strength value for the given entry is below a threshold. Otherwise, in response to detecting no entries of the first table have a strength value below the threshold, the first predictor allocates an entry in the second table for the received fetch address. When an indication of a target address for the received fetch address is a return address for a function call, a third predictor allocates an entry of a third table with the received fetch address.

Next fetch prediction return table

Scheduler for AMP architecture with closed loop performance controller

Growing community of inventors

Cupertino, CA, United States of America

Constantin Pistol