Arm Limited

Arm Limitied

Conrado Blasco Allue

Stephen John Hill

Glen Andrew Harris

Andrew Brookfield Swaine

Paul Kimelman

Richard Roy Grisenthwaite

David James Williamson

James Nolan Hardage

Michael John Williams

Richard Slobodnik

Robert Gregory McDonald

An out-of-order processorgroups program instructions together to control their commitment to complete processing. If an instruction within a group has a source operand dependent upon a plurality of destination operands of other instructions then this is identified as a size mismatch hazard. When the program instruction having the size mismatch hazard reaches a commit point within the processor, then it is flushed together with any speculatively executed succeeding program instructions. Furthermore, the group of program instructions containing the program instruction containing the program instruction having the size mismatch is divided into a plurality of groups of program instructions each containing a single program instruction which are then replayed through the processing mechanisms.

Size mis-match hazard detection

An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register of a double precision size may alias with two single precision registers being used as destinations of one or more preceding program instructions. In order to track this data dependency the double precision register may be remapped into a micro-operation specifying two single precision registers as its source register. In this way, scheduling circuitry may use its existing hazard detection and management mechanisms to handle potential data hazards and dependencies. Not all program instructions having such data hazards between registers of different sizes are handled by this source register remapping. For these other program instructions a slower mechanism for dealing with the data dependency hazard is provided. This slower mechanism may, for example, be to drain all the preceding micro-operations from the execution pipelines before issuing the micro-operation having the data hazard.

Renaming wide register source operand with plural short register source operands for select instructions to detect dependency fast with existing mechanism

A method and a data processing apparatus operable to process instructions from a plurality of instruction sets, the plurality of instruction sets each sharing a sub-set of common instructions and each having a remaining set of instructions is disclosed. The data processing apparatus comprises: a plurality of decode units, each decode unit being operable to only decode the remaining set of instructions from a corresponding one of the plurality of instruction sets; and a common decode unit operable to decode a number of the sub-set of common instructions from each of the plurality of instruction sets. This enables the common instructions from each instruction set to be decoded by the common decode unit. Hence, the logic which would otherwise be duplicated in each of the individual decode units for each instruction set can be removed from those decode units and provided just once in the common decode unit. Accordingly, this can significantly reduce the amount of logic duplicated in the decoder units which, in turn, reduces the amount chip area required to support decoding and reduces power consumption. Also, since the decode units are no longer required to support the decoding of such a high number of different instructions, the complexity of each decode unit can be reduced, which can result in increased performance during decode.

Multiple instruction set decoding

A data processing systemis described having a central processing unitand a diagnostic mechanismThe central processing unitis switchable into a power-down mode from which it may resume into a normal operation mode. When the central processing unitresumes into the normal operation mode, execution of program instructions is inhibited by the diagnostic mechanismto allow the diagnostic mechanism to be appropriately programmed such that the immediate power-up code and operations can be properly diagnosed. The requirement to prevent program instruction execution on power-up is programmed by writing to a latchwithin the diagnostic mechanismprior to the power-down. The prevention of program execution may be achieved, for example, by generation of a halt request or by extending the time period for which the central processing unitis held in reset following power-up.

Forced diagnostic entry upon power-up

A data processing apparatus is provided having a plurality of functional units. At least one of the functional units is operable to perform data processing operations and at least a subset of the plurality of functional units have at least one of a respective co-processor register for storing configuration data and a respective debug register for storing debug data. A debug controller outputs debug data and co-ordinates debug operations. A configuration ring-bus provides a ring path for communication of configuration instructions between a first ring sequence of the plurality of functional units and a debug ring-bus provides a ring path for communication of the debug data between a second ring sequence of the plurality of functional units. Separate provision of the debug ring-bus and the configuration ring-bus provides independent access to the co-processor register and to the debug register.

Provision of debug via a separate ring bus in a data processing apparatus

A data processing apparatus is operable in a either a self-test mode or an operational mode. The apparatus comprises a plurality of functional units, at least one of the functional units being operable to perform data processing operations and at least a subset of the plurality of functional units having at least one of a respective co-processor register for storing configuration data, a respective debug register for storing debug data and a respective functional unit memory. A memory self-test controller operable in the self-test mode to output self-test data for performing access operations to confirm correct operation of the functional unit memory. A debug controller outputs debug data and co-ordinates debug operations, the debug controller being one of the plurality of functional units. In the operational mode a configuration ring-bus provides a ring path for communication of configuration instructions between a first ring sequence of the plurality of functional units whereas a debug ring-bus provides a ring path for communication of the debug data between a second ring sequence of the plurality of functional units. The first ring sequence is identical to the second ring sequence and the data processing apparatus is operable in the self-test mode to couple the configuration ring-bus and the debug ring-bus to provide a combined data path for communication of self-test data between the plurality of functional units.

Memory self-test via a ring bus in a data processing apparatus

Within a system-on-chip devicehaving multiple processing circuitsone processing circuitmay serve to perform diagnostic operations upon another processing circuitby accessing diagnostic data relating to that other circuit. Thus, one processor may, for example, control and perform halting mode type diagnostic or code profiling upon another.

Diagnostic mechanisms within multi processing systems

Within a multiple instruction pipeline data processing system which supports predication instructions, program instructions are initially decoded upon the assumption that they are predicated. A predication signal is generated within the instruction decoder stages when a predication instruction is detected. The presence or absence of this predication signal can then be used to correct any decoding which has been performed upon the basis of an assumption that the program instructions are predicated. The predication instruction can predicate a variable number of following instructions. The predication instruction can issue in parallel with an instruction which it predicates and yet the proper identification of the predication instruction need not be confirmed until at least some decoding has been performed upon the other program instruction.

Decoding predication instructions within a superscaler data processing system

A system-on-chip integrated circuitis provided with multiple data processing circuitseach with an associated diagnostic interface circuitconnected via a diagnostic transaction busto a diagnostic transaction master circuit. The diagnostic master transaction circuitissues diagnostic transaction requests to the diagnostic interface circuits. If the associated data processing circuitsare powered-down, or otherwise non responsive, then the diagnostic interface circuitreturns a diagnostic bus transaction error signal to the diagnostic transaction master circuit. A sticky-bit latchwithin each diagnostic interface circuitserves to record a power-down event and force generation of the diagnostic bus transaction error signal until that sticky bit is cleared by the diagnostic mechanisms. This ensure the diagnostic mechanisms are made aware of the power-down event so they may take any appropriate remedial action that might be necessary as a result of that power-down event.

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Austin, TX, United States of America

Conrado Blasco Allue