Xilinx, Inc.

Conrad A Theron

Donald H St Pierre, Jr

Carl H Carmichael

Arthur H Khu

Farshid Shokouhi

Edwin W Resler

Mihai G Statovici

Pushpasheel Tawade

Michael Leonard Simmons

Arun K Mandhania

Chakravarthy K Allamsetty

Walter H Edmondson

Thach-Kinh Le

A separate program power input is provided to a programmable logic array's memory to permit it to be programmed independently of printed circuit board power. Means are provided to isolate the program power input from the array's programmable logic circuit. Means are further provided to isolate the memory from the programmable logic circuit. The program power is not connected directly or indirectly to the programmable logic circuit thereby permitting the use of low-power devices to program the memory without connecting the printed circuit board to a power supply.

Integrated circuit device programming with partial power

Method, apparatus, and computer readable medium for generating test vectors for an integrated circuit (IC) under test is described. In one example, a test function is specified using at least one elementary function that encapsulates program code associated with an architecture of the IC under test. An engine is configured with device description data for the IC under test. The engine is executed with the test function as parametric input to generate the test vectors. In one example, the IC under test comprises a programmable logic device (PLD) and the test vectors include configuration data for configuring a pattern in the PLD and at least one test vector for exercising the pattern. The test vectors may be applied directly to the device or through automatic test equipment (ATE). Alternatively, the test vectors may be applied to a IC design simulation of the device.

Method and apparatus for generating test vectors for an integrated circuit under test

According to the invention, a JTAG-compliant chip having a controller that receives data provided on the TDI input pin and forms parallel address and data instructions and passes the data through IO pins to the non-JTAG chip is able to verify whether the data was correctly received by the non-JTAG chip by reading back the data and comparing to the original data. A status bit or bits are shifted out on a TDO pin and used to determine what data will be shifted in next.

Structure and method for verifying data in a non-JTAG device from a JTAG device with microcontroller

According to the invention, a JTAG-compliant chip is further provided with a controller that receives data provided on the TDI input pin, forms parallel address and data instructions and passes the data through IO pins to the non-JTAG chip without requiring the data to go through the boundary scan register chain of the JTAG-compliant chip. This controller is used to program, erase, and read the other chip. For a non-JTAG flash memory device, the controller in the JTAG-compliant chip generates the necessary programming signal sequences, and applies them to the non-JTAG chip without going through the JTAG boundary scan circuitry.

Structure and method for writing from a JTAG device with microcontroller to a non-JTAG device

A method is disclosed for selectively overlaying portions of a default firmware code for a microcontroller of an FPGA interface device. The FPGA interface device includes a microcontroller, an on-board FPGA, and a memory having first and second pages. Upon initial power-up of the interface device, the default firmware code is loaded into the first memory page. Thereafter, the microcontroller executes instructions received from a host system using the firmware code loaded in the first memory page. Where it is desired to update or modify the firmware code, an overlay code is stored in the second memory page. The overlay code corresponds to selected portions of the default firmware code. Overlay flags are asserted for each of the selected portions of the default firmware code for which a corresponding overlay code is loaded in the second memory page. Then, during execution of subsequent instructions received from the host system, the overlay code is substituted for corresponding portions of the default firmware code for which the overlay flags are asserted.

Method and apparatus for changing execution code for a microcontroller on an FPGA interface device

An FPGA interface device includes a microcontroller having a parallel port, a serial memory having an output port, and an on-board FPGA having a serial port coupled to the output port of the serial PROM and having a parallel port coupled to the parallel port of the microcontroller. The configuration design for the FPGA interface device's on-board FPGA and the firmware code for the interface device's microcontroller are stored in the serial memory. Upon power-up, the on-board FPGA reads the configuration design from the serial memory, and then configures itself accordingly. After properly configured, the on-board FPGA serially reads the microcontroller firmware code from the serial memory, parallelizes the firmware code, and thereafter enables the microcontroller to access the resulting parallel firmware code. Since both the on-board FPGA configuration design and the microcontroller firmware code are stored in a single memory, the dedicated parallel memory previously used to store the microcontroller firmware code may be eliminated, thereby advantageously conserving printed circuit board area.

Embedding firmware for a microprocessor with configuration data for a field programmable gate array

A method is disclosed for communicating with an FPGA interface device having a microcontroller when the on-board microcontroller is not responsive to commands from a host system. If the host system determines that the microcontroller is not responsive to commands, the host system sends a null character to the interface device at a predetermined baud rate which is significantly distinguishable from baud rates normally used for communicating with the microcontroller. A logic circuit on the interface device monitors the baud rate of incoming data, and if a null character at the predetermined baud rate is detected, the logic circuit toggles the reset pin of the microcontroller. In response thereto, the microcontroller re-boots itself, and is thereafter able to communicate with the host system. Additional commands are provided to the interface device by using other baud rates which are significantly distinguishable from the baud rates normally used.

Method for resisting an FPGA interface device

A system and method for reading back data from a programmable logic device (PLD). A clock offset table having one or more clock offset values is constructed. Each clock offset value indicates a relative clock cycle at which a selected bit read from the device is saved and sent to a host computer. The data is read from the PLD at a rate of one bit per readback clock cycle, and the readback clock cycles are counted as the bits are read from the device. When the count of readback clock cycles equals an offset, the bit is selected and saved.

System and method for reading data from a programmable logic device

A method is disclosed for disguising a device's connection to a USB port of, for instance, a host system such as a personal computer or workstation. A device having a microcontroller is connected to a host system using a USB port connection. A switch is coupled between one of the data pins of the USB port and a supply voltage. When the device is connected to the host system via the USB port, the switch is turned off so as not to pull a USB data pin to the supply voltage, and thereby prevents the host system from recognizing that a peripheral device is attached to the USB port. The switch is maintained in a non-conductive state until the microcontroller on the device is booted up and has retrieved identification codes associated with the device and is then turned on. In this manner, the host system does not detect the connection of the device to the host system's USB port until the device is ready to provide suitable identification codes to the host system.

Method of disguising a USB port connection

A method is disclosed for reconfiguring an on-board FPGA of an interface device without resetting the interface device. The FPGA interface device also includes a microcontroller, and the on-board FPGA has a serial data port coupled to a first, non-volatile memory and a parallel data port coupled to a second memory, which may be a volatile memory. The default configuration design is stored in the non-volatile memory. The on-board FPGA is initially in a serial configuration mode such that upon power-up, the on-board FPGA looks to the first memory via its serial port for the configuration design. Where it is desired to reconfigure the on-board FPGA, a new configuration design is stored in the second memory, and the on-board FPGA is instructed to reconfigure itself in parallel mode. In response thereto, the on-board FPGA looks to the second memory via its parallel port, retrieves the new configuration design, and then reconfigures itself accordingly.

Method for reconfiguring a field programmable gate array from a host

A method is disclosed for alerting a user of a low power condition on, for instance, an FPGA interface device. An interface device having a microcontroller and an associated power plane for powering the microcontroller and other component on the interface device includes a detection circuit coupled to monitor the voltage level of the associated power plane. When the voltage level of the voltage plane falls below a predetermined threshold voltage, the detection circuit sends a low power flag to a host system. The low power flag, which is preferably sent to the host system using a USB port connection, alerts the host system of the low power condition on the interface device. The predetermined threshold voltage is selected to be a suitable amount higher than the minimum operating voltage for the microcontroller so as to allow sufficient time for the microcontroller to send the low power flag to the host system. In response thereto, the host system may take suitable action such as, for instance, alerting the user, resetting the microcontroller, aborting a download process, and so on.

Method for detecting low power on an FPGA interface device

The present invention provides an apparatus for converting logic signals of a first voltage level to logic signals of a second voltage level in response to a control signal indicative of whether logic signals on an associated target device are of the first or second voltage level. An output configuration includes a de-multiplexer having an input terminal coupled to receive an output signal of an associated logic circuit, a control terminal coupled to receive a control signal, and first and second output terminals, the first de-multiplexer output terminal being connected to the target device. A switch coupled between the second de-multiplexer output terminal and the target device has a control terminal coupled to receive the control signal. When the control signal is in a first state, a voltage drop across the switch converts the logic signals of the first voltage level to logic signals of the second voltage level. When the control signal is in a second state, the switch is not conductive, and the logic signals of the associated logic circuit are provided directly to the target device.

Growing community of inventors

San Jose, CA, United States of America

Conrad A Theron