International Business Machines Corporation

Conrad A Barile

Hazara Singh Rathore

Du Binh Nguyen

Birendra N Agarwala

Jawahar P Nayak

Chih-Chao Yang

Lawrence Alfred Clevenger

Thomas M Shaw

Xiao Hu Liu

Conal Eugene Murray

Vincent James McGahay

Kaushik Chanda

Hormazdyar M Dalal

Michael Wayne Lane

Paul Stephen McLaughlin

Ernest N Levine

Andrew P Cowley

Robert Daniel Edwards

James S Makris

John L Forneris

Joseph Regh

Arunachala Nagarajan

Brett H Engle

John F McGrath

Robert M Brill

Goerge R Goth

Raj K Raheja

The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for a layer within chips comprising a semiconductor wafer lot. If only one mode is calculated, that is the best calculated mode. If multiple modes can be calculated, a best mode that most accurately represents dielectric breakdown for the semiconductor wafer lot is determined. Premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation from the best calculated mode.

Method for prediction of premature dielectric breakdown in a semiconductor

The present invention provides an interconnect structure that includes a diffusion barrier which is positioned within the structure in a fashion that increases the reliability and lifetime of the interconnect structure.

Via barrier layers continuous with metal line barrier layers at notched or dielectric mesa portions in metal lines

A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.

Stacked via-stud with improved reliability in copper metallurgy

A very high current ion implanted emitter is formed in a diffused base. Windows are made through the silicon nitride and silicon dioxide layes to both the base contact and the emitter regions using a resist mask. These regions are then protected by resist and the collector contact window is opened through the remainder of the silicon dioxide layer to the reach through region. A screen oxide is then grown in all the exposed areas after the removal of the resist mask. A resist mask is applied which covers only the base and Schottky anode regions. Arsenic is then implanted through the exposed screened areas followed by an etch back step to remove the top damaged layer. With some remaining screen oxide serving as a cap, the emitter drive-in is done.

Bipolar transistor fabrication process with an ion implanted emitter

A region in an integrated circuit substrate is formed by first ion implanting impurities of a selected conductivity-determining type into a semiconductor substrate through at least one aperture in a masking electrically insulative layer, and then diffusing a conductivity-determining impurity of the same type through the same aperture into said substrate. The method has particular application when the electrically insulative layer is a composite of two layers, e.g., a top layer of silicon nitride and a bottom layer of silicon dioxide and the aperture is thus a pair of registered openings respectively through said silicon nitride and silicon dioxide layers, and the aperture through the silicon dioxide layer has greater lateral dimensions than that in the silicon nitride layer to provide an undercut beneath the silicon nitride ion implantation barrier layer.

Method of forming an integrated circuit region through the combination

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Wappingers Falls, NY, United States of America

Conrad A Barile