Intel Corporation

Conor P Puls

Tahir Ghani

Abhishek A Sharma

Mauro J Kobrinsky

Bernhard Sell

Wilfred Gomes

Kevin Fischer

Doug B Ingerly

Mohammad Enamul Kabir

Keith Zawadzki

Babita Dhayal

Avyaya Jayanthinarasimham

Hannes Greve

Han Li

Mukund Bapna

Oleg Golonzka

Leonard P Guler

Christopher J Wiegand

Justin Brockman

Angeline Smith

Tofizur Rahman

Daniel Ouellette

Juan G Alzate-Vinasco

Sukru Yemenicioglu

Andrew Smith

Pedro Quintero

Makram Abd El Qader

Stephen Wu

Integrated circuit structures having recessed self-aligned deep boundary vias are described. For example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts extends over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A backside metal routing layer is extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. A conductive structure couples the backside metal routing layer to one of the one or more of the plurality of trench contacts. The conductive structure includes a pillar portion in contact with the one of the one or more of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

Integrated circuit structure with recessed self-aligned deep boundary via

Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and contacting a support substrate coupled to the bonding layer. Such devices systems, and methods may further include via structures having the same material system as the guard ring structure and also extending through the interconnect, the device, and bonding layers and contacting a support substrate.

Moisture hermetic guard ring for semiconductor on insulator devices

Described herein are IC devices that include TFT based memory arrays on both sides of a layer of logic devices. An example IC device includes a support structure (e.g., a substrate) on which one or more logic devices may be implemented. The IC device further includes a first memory cell on one side of the support structure, and a second memory cell on the other side of the support structure, where each of the first memory cell and the second memory cell includes a TFT as an access transistor. Providing TFT based memory cells on both sides of a layer of logic devices allows significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, significantly reducing the footprint area of the memory array with a given memory cell density.

Thin film transistor based memory cells on both sides of a layer of logic devices

A memory device method of fabrication that includes a first electrode having a first conductive layer including titanium and nitrogen and a second conductive layer on the first conductive layer that includes tantalum and nitrogen. The memory device further includes a magnetic tunnel junction (MTJ) on the first electrode. In some embodiments, at least a portion of the first conductive layer proximal to an interface with the second conductive layer includes oxygen.

Magnetic memory devices with layered electrodes and methods of fabrication

Growing community of inventors

Portland, OR, United States of America

Conor P Puls