Fujitsu Corporation

Connie M Wong

Solomon I Beilin

William T Chou

Larry Louis Moresco

David A Horine

David G Love

Michael G Lee

Wen-chou Vincent Wang

A method for electrically coupling electrode pads comprising forming a reflowed solder bump on a first electrode pad supported by a first substrate. The reflowed solder bump includes a solder material having a solder melting temperature. The method further includes forming a second electrode pad on a second substrate. The second electrode pad has an electrode structure defined by at least one converging continuous arcuate surface terminating in an apex and having an electrode material whose melting temperature is greater than the solder melting temperature of the solder material. The solder bump is heated to reflow or to soften the solder material, and subsequently the apex of the second electrode pad is pressed or inserted into the heated solder bump to couple the first electrode pad to the second electrode pad. A method for solder bump reflow comprising pressing or inserting the apex of an electrode into a reflowed solder bumps, and then reflowing solder material of the reflowed solder bump. A semiconductor assembly including a semiconductor device having an electrode pad coupled to a semiconductor substrate and comprising an electrode structure defined by a pair of arcuate surfaces generally tangentially terminating in an apex.

Multilayer interconnection and method

Interconnect structures and methods for making interconnect structures are disclosed. A typical interconnect structure has a tapered first end portion having a first substantially planar surface and a concave surface adjacent to the first planar surface. A second end portion of the interconnect structure includes a second substantially planar surface. The second planar surface has a larger area than the first planar surface. An intermediate portion is disposed between the first end portion and the second end portion.

Conductive interconnect structures and methods for forming conductive interconnect structures

An interconnect structure for connecting an integrated circuit (IC) chip to a supporting substrate is described. The supporting substrate serves to communicate signals between the IC chip and the 'outside world,' such as other IC chips. In one embodiment, the interconnect structure comprises an interconnect substrate having a first post disposed on one of its surfaces and a second post disposed on another of its surfaces. One post is for contacting the IC chip and the other is for contacting the major substrate. Each post comprising an elongated body having top and bottom ends, with the bottom end being mounted to one of the substrate surfaces and the top end having a substantially flat surface which is substantially co-planer with the substrate surface. The interconnect substrate further comprises a means for de-concentrating the mechanical stain present at one or both of the top and bottom ends of each post. The first and second posts are electrically coupled to one anther so that an electrical signal may pass from IC chip to the supporting substrate, and vice-versa.

Wire interconnect structures for connecting an integrated circuit to a

Methods of constructing a wire interconnect structure on a substrate are described. The methods broadly comprise the steps of depositing a spacer layer on a surface of the substrate, depositing a mask layer on the spacer layer, and removing a first portion of the mask layer overlying a desired area on the substrate surface to expose the spacer layer underlying the first portion of the mask layer. The methods further comprise the step of etching the structure such that a first portion of the spacer layer overlaying the desired area is removed and such that a portion of the desired area is exposed, and the step of depositing a first conductive material on the exposed portion of the desired area such that a conductive post is formed on the substrate surface and mounted to the desired area. Some of the disclosed methods comprise additional steps for forming an interconnect structure on the opposite surface of the substrate and providing an electrical interconnect means between the two interconnect structures. Additionally, some of the disclosed methods comprise steps for forming fillets around the conductive post at the substrate surface.

An interconnect structure for connecting an integrated circuit (IC) chip to a supporting substrate is described. The supporting substrate serves to communicate signals between the IC chip and the 'outside world,' such as other IC chips. In one embodiment, the interconnect structure comprises an interconnect substrate having a first post disposed on one of its surfaces and a second post disposed on another of its surfaces. One post is for contacting the IC chip and the other is for contacting the major substrate. Each post comprises an elongated body having top and bottom ends, with the bottom end being mounted to one of the substrate surfaces and the top end having a substantially flat surface which is substantially co-planer with the substrate surface. The interconnect substrate further comprises a device for de-concentrating the mechanical stain present at one or both of the top and bottom ends of each post. The first and second posts are electrically coupled to one anther so that an electrical signal may pass from IC chip to the supporting substrate, and vice-versa.

Growing community of inventors

Fremont, CA, United States of America

Connie M Wong