Smsc Holdings Sarl

Shenzhen Sts Microelectronics Co., Ltd.

CongQing Xiong

Hongming An

Heng Wang

Wei Fu

James Ho

Christopher T Thomas

Jun Ye

Weiguo Ge

Various techniques are provided to generate a plurality of reference clock signals using a single reference clock signal generator. In one example, a clock signal generation system includes a reference clock signal generator adapted to provide a reference clock signal. The system also includes a plurality of dividers adapted to divide the reference clock signal using different ratios to provide a plurality of communication port clock signals. The system also includes a plurality of different communication ports adapted to receive the communication port clock signals and adapted to operate in accordance with different communication protocols using the communication port clock signals.

System and method for generating clock signal for a plurality of communication ports by selectively dividing a reference clock signal with a plurality of ratios

Various techniques are provided to facilitate a detection system to detect a presence of an externally coupled receiver device, such as a universal serial bus (USB) device. In one example, the system generates a reference current and passes the reference current via a conductor to a shared buffer circuit. The shared buffer circuit is adapted to selectively pass the reference current or a communication signal to the externally coupled receiver device. The system switches between a detect mode where the reference current is provided to the externally coupled receiver device and between a communicate mode where the reference current is blocked and the communication signal is provided to the externally coupled receiver device. The system monitors a voltage value of the conductor and the system monitors a time for the voltage value to reach a pre-determined threshold value in response to the reference current. The system detects a presence of the externally coupled receiver device based on the monitored time.

Detection system and methods

Various techniques are provided to detect a state of a communication signal. In one example, a method of detecting a state of a signal includes receiving a differential communication signal comprising a positive portion and a complementary negative portion. The method also includes generating a common mode voltage signal from the positive portion and the negative portion of the communication signal. The method also includes rectifying the positive portion and the negative portion of the communication signal to provide a rectified signal. The method also includes comparing the common mode voltage, signal with the rectified signal. The method also includes generating a high frequency detect signal in response to the comparing. The method also includes determining whether the communication signal is in an idle state or a high frequency state based on the high frequency detect signal.

High frequency and idle communication signal state detection

Various techniques are provided to detect a state of a communication signal. In one example, a method of detecting a state of a signal includes receiving a differential communication signal comprising a positive portion and a complementary negative portion. The method also includes filtering the positive portion of the communication signal through a first low pass filter to provide a filtered positive portion of the communication signal. The method also includes filtering the negative portion of the communication signal through a second low pass filter to provide a filtered negative portion of the communication signal. The method also includes comparing the filtered positive portion of the communication signal with an internal reference voltage. The method also includes comparing the filtered negative portion of the communication signal with the internal reference voltage. The method also includes generating a low frequency detect signal in response to the comparing operations to indicate whether the communication signal is in a low frequency state.

Low frequency communication signal state detection

Techniques are provided to serialize and delay parallel input data signals and are particularly useful for low power applications. In one example, a device includes a plurality of data input ports adapted to receive N parallel single-ended input data signals, and a clock input port adapted to receive a clock signal substantially synchronized with the parallel single-ended input data signals. The device also includes a cell adapted to serialize the parallel single-ended input data signals to provide N/2 first serial differential output data signals in response to the clock signal, delay the parallel single-ended input data signals, and serialize the delayed parallel single-ended input data signals to provide N/2 delayed second serial differential output data signals in response to the clock signal. The delayed second serial differential output data signals are delayed relative to the first serial differential output data signals. The device also includes a plurality of output ports.

High speed low power cell providing serial differential signals

A current sense amplifier including a transconductance amplifier to measure a current passing through a sense resistor and generate a reference current indicative of the measured current. A current mirror circuit is connected to the transconductance amplifier and receives the reference current for amplification to generate an amplified output current. A cascode circuit is connected serially to the current mirror circuit to boost an output impedance for the amplifier at the output of the generated amplified output current. The current mirror circuit and cascode circuit of the current sense amplifier are each formed from a pair of transistors sharing a common control node, with the transistors realized using with bipolar or MOS technology.

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Shenzhen, China

CongQing Xiong