Sun Microsystems, Inc.

Intel Corporation

Synopsys, Inc.

Cavendish Kinetics Limited

Synopsis Incorporated

Qorvo Us, Inc.

Cong Quoc Khieu

Robertus Petrus Van Kampen

Shifeng Yu

Richard Lee Knipe

James D Huffman

Yanjun Ma

Vikram Joshi

Jaideep Mavoori

Louise Gu

Fabrizio Romano

Der-Ren Chu

Lan Lee

Xin Liu

Kailashnath Nagarakanti

Kathakali Debnath

Karl F Smayling

Anurag Sah

Cornelius Petrus Elisabeth Schepens

Chaidir Tjakra

Zhigang Han

Ivana Cappellano, Legal Representative

Ivana Cappellano

James Douglas Huffman

The present invention generally relates to a mechanism for testing a MEMS hysteresis. A power management circuit may be coupled to the electrodes that cause the movable plate that is disposed between the electrodes in a MEMS device to move. The power management circuit may utilize a charge pump, a comparator and a resistor ladder.

Internally generated DFT stepped hysteresis sweep for electrostatic MEMS

The present invention generally relates to a method of operating a MEMS DVC while minimizing impact of the MEMS device on contact surfaces. By reducing the drive voltage upon the pull-in movement of the MEMS device, the acceleration of the MEMS device towards the contact surface is reduced and thus, the impact velocity is reduced and less damage of the MEMS DVC device occurs.

Method and technique to control MEMS DVC control waveform for lifetime enhancement

The present invention generally relates to a DVC having a charge-pump coupled to a MEMS device. The charge-pump is designed to control the output voltage delivered to the electrodes, such as the pull-in electrode or the pull-off electrode, that move the switching element within the MEMS device between locations spaced far from and disposed closely to the RF electrode.

Two-state charge-pump control-loop for MEMS DVC control

The present invention generally relates to methods for increasing the lifetime of MEMS devices by reducing the number of movements of a switching element in the MEMS device. Rather than returning to a ground state between cycles, the switching element can remain in the same state if both cycles necessitate the same capacitance. For example, if in both a first and second cycle, the switching element of the MEMS device is in a state of high capacitance the switching element can remain in place between the first and second cycle rather than move to the ground state. Even if the polarity of the capacitance is different in successive cycles, the switching element can remain in place and the polarity can be switched. Because the switching element remains in place between cycles, the switching element, while having the same finite number of movements, should have a longer lifetime.

MEMS lifetime enhancement

Apparatus, systems, and methods may include managing electrostatic discharge events by using a semiconductor device having a non-aligned gate to implement a snap-back voltage protection mechanism. Such devices may be formed by doping a semiconductor substrate to form a first conductive region as a well, forming one of a source region and a drain region in the well, depositing a layer of polysilicon on the substrate to establish a gating area that does not overlap the one of the source region and the drain region, and forming an integrated circuit supported by the substrate to couple to the one of the source region and the drain region to provide snap-back voltage operation at a node between the integrated circuit and the source or drain region. Additional apparatus, systems, and methods are disclosed.

Electrostatic discharge management apparatus, systems, and methods

Embodiments disclosed herein generally relate to switches that utilize micro-electromechanical systems (MEMS). By replacing transistors in many devices with switches such as MEMS switches, the devices may be used for logic applications. MEMS switches may be used in devices such as FPGAs, NAND devices, nvSRAM devices, AMS chips and general memory logic devices. The benefit of utilizing MEMS devices in place of transistors is that the transistors utilize more space on the chip. Additionally, the MEMS devices can be formed in the BEOL without having any negative impacts on the FEOL or necessitating the use of additional layers within the chip.

Binary logic utilizing MEMS devices

Apparatus, systems, and methods may include providing a power-on reset function to many types of receiving circuitry, including radio frequency identification (RFID) tag processing circuitry. Thus, the power-on reset function may be realized by applying a supply voltage to a power-on reset circuit coupled to RFID tag processing circuitry. Operations may include sensing a first current substantially independent of the supply voltage, sensing a second current substantially dependent on the supply voltage, and indicating a power-on reset condition based on a comparison between the first current and the second current. Additional apparatus, systems, and methods are disclosed.

Radio frequency identification device power-on reset management

Apparatus, systems, and methods may include providing a power-on reset function to many types of receiving circuitry, including processors, memories, and radio frequency identification (RFID) tag processing circuitry. Thus, the power-on reset function may be realized by applying a supply voltage to a power-on reset circuit coupled to the processing circuit of an RFID tag. Additional activity may include sensing a first current substantially independent of the supply voltage, sensing a second current substantially dependent on the supply voltage, and indicating a power-on reset condition based on a comparison between the first current and the second current. Additional apparatus, systems, and methods are disclosed.

Power-on reset apparatus, systems, and methods

Apparatus, systems, and methods may include managing electrostatic discharge events in radio frequency identification (RFID) devices by using a semiconductor circuit having a non-aligned gate to implement a snap-back voltage protection mechanism. Such circuits may be formed by doping a semiconductor substrate to form a first conductive region as a well, forming one of a source region and a drain region in the well, depositing a layer of polysilicon on the substrate to establish a gating area that does not overlap the one of the source region and the drain region, and forming an integrated circuit including an RFID circuit that is supported by the substrate to couple to the one of the source region and the drain region to provide snap-back voltage operation at a node between the integrated circuit and the source or drain region. Additional apparatus, systems, and methods are disclosed.

Radio frequency identification device electrostatic discharge management

Disclosed is a method and circuit for generating an average binary code from at least two input binary codes. The circuit may be employed in an integrated circuit having first and second circuits for generating binary codes aand b, respectively. In one embodiment, the circuit asynchronously generates a binary code crepresenting an average of the binary codes aand bgenerated by the first and second circuits, respectively.

Average code generation circuit

Disclosed is a method and circuit for variably controlling a delay line for a read data capture timing window. In one embodiment, the circuit includes a variably controlled delay circuit coupled to a FIFO. The variably controlled delay circuit receives an input strobe signal. The variably controlled delay circuit also receives a multibit control code. The variably controlled delay circuit transmits the input strobe signal after a time delay, wherein the time delay varies according to the multibit control code. The FIFO is coupled to the variably controlled delay circuit and receives the time delayed strobe signal therefrom. The FIFO receives an input data bit signal. The FIFO stores the input data bit signal in response to receiving the time delayed strobe signal.

Variably controlled delay line for read data capture timing window

A CPU clock signal generated from a phase lock loop (PLL) circuit and a feedback signal of the PLL circuit are used in generating a JBUS clock signal. The CPU clock signal and the feedback signal include the same amount of static phase offset introduced by the PLL circuit. The CPU clock signal and the feedback signal are input to an alignment detection circuit and used in generating the JBUS clock signal. In one embodiment, the JBUS clock signal is generated in synchronization with the CPU clock signal and having the frequency of the feedback signal. The present invention reduces or eliminates misalignment of the leading edge of the JBUS signal with reference to a specific leading edge of the CPU clock signal due to the presence of static phase offset introduced by the PLL circuit.

Method and apparatus for static phase offset correction

Disclosed is an input/output (IO) device for transmitting an input data bit signal. In one embodiment, the IO device includes an IO device input node for receiving the input data bit signal and an IO device output node. The IO device also includes a driver coupled between the IO device input node and the IO device output node. The driver includes at least one FET that defines a gate oxide voltage limit. The driver receives a supply voltage and the input data bit signal. The driver charges and discharges the IO device output node to the supply voltage and ground, respectively, in response to driver receiving the supply voltage and the input data bit signal. The supply voltage is greater than the gate oxide voltage limit.

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San Jose, CA, United States of America

Cong Quoc Khieu