Mediatek Singapore Pte. Ltd.

Iflytek Co., Ltd.

University of Science and Technology of China

Cong Liu

Guoping Hu

Yu-Kai Chou

Qingfeng Liu

Jia Pan

Ming Wang

Chih-Chien Huang

Jun Du

Zhiguo Wang

Kun Lan

Si Wei

Haikun Wang

Jianqing Gao

Shifu Xiong

Jiajia Wu

Jinshui Hu

Lirong Dai

Jianshu Zhang

A PLL circuit generates an output signal having an output frequency and includes a voltage-to-current conversion circuit, a frequency compensation circuit, and an ICO. The voltage-to-current conversion circuit is configured to generate a first control current according to a control voltage, wherein the control voltage is generated according to a reference signal and a feedback signal derived from the output signal. The frequency compensation circuit is configured to generate a second control current according to the control voltage. The ICO generates the output signal according to an oscillation current, wherein the oscillation current is a sum of the first control current and the second control current. In response to the frequency compensation circuit detecting that the control voltage is out of a predetermined range, the second control current is controlled to be negatively correlated with the output frequency.

Phase-locked loop circuit

A speech recognition method and related products are provided. The method includes acquiring a to-be-recognized speech and a configured hot word library; determining, based on the to-be-recognized speech and the hot word library, an audio-related feature used at a current decoding time instant; determining, based on the audio-related feature, a hot word-related feature used at the current decoding time instant from the hot word library; and determining, based on the audio-related feature and the hot word-related feature, a recognition result of the to-be-recognized speech at the current decoding time instant.

Speech recognition method, apparatus and device, and storage medium

A device for correcting a duty cycle, comprising: a duty adjustor circuit, configured to receive an input clock signal and a tuning signal, to generate an output clock signal; a first charge pump, configured to charge a first capacitor for a predetermined time period to generate a first voltage; a second charge pump, configured to charge a second capacitor for a time period corresponding to the duty cycle of the output clock signal to generate a second voltage; a first sampling and hold circuit, configured to sample the first voltage to generate a first sampled voltage; a second sampling and hold circuit, configured to sample the second voltage to generate a second sampled voltage; and an error amplifier, configured to generate the tuning signal according to a difference value between the first sampled voltage and the second sampled voltage.

Device for correcting duty cycle and method for correcting duty cycle

A method, an apparatus and a device for converting a whispered speech, and a readable storage medium are provided. The method is implemented based on the whispered speech converting model. The whispered speech converting model is trained in advance by using recognition results and whispered speech training acoustic features of whispered speech training data as samples and using normal speech acoustic features of normal speech data parallel to the whispered speech training data as sample labels. A whispered speech acoustic feature and a preliminary recognition result of whispered speech data are acquired, then the whispered speech acoustic feature and the preliminary recognition result are inputted into a preset whispered speech converting model to acquire a normal speech acoustic feature outputted by the model. In this way, the whispered speech can be converted to a normal speech.

Whispering voice recovery method, apparatus and device, and readable storage medium

A method for recognizing a character includes: obtaining a character; converting the character into a radical based character recognition result, where the radical based character recognition result comprises symbols indicating radicals of the character and a structure of the radicals of the character; and recognizing the character based on the radical based character recognition result.

Method, apparatus and storage medium for recognizing character

An analog-to-digital converter is provided. The analog-to-digital converter includes a sampling-voltage providing circuit, a first comparison circuit, a second comparison circuit, and an encoder circuit. The sampling-voltage providing circuit provides a group of first comparison voltages and a group of second comparison voltages. The first comparison circuit performs a first comparison operation to an analog-signal input quantity according to the group of first comparison voltages to generate a first comparison digital quantity. The second comparison circuit selects second comparison voltages among the group of second comparison voltages according to the first comparison digital quantity and performs a second comparison operation to the analog-signal input quantity according to the selected second comparison voltages to generate a second comparison digital quantity. The encoder circuit encodes the first comparison digital quantity and the second comparison digital quantity and generates a digital quantity corresponding to the analog-signal input quantity.

Analog-to-digital converters and pipeline analog-to-digital converters

A multiplying digital-to-analog converter (MDAC) is provided. The MDAC includes a sub DAC decoding circuit, a capacitor-switch circuit, and an operation amplifier circuit. The capacitor-switch circuit includes at least two sampling capacitor sets which are coupled in parallel. The number of sampling capacitors in one of the sampling capacitor sets is larger than or equal to two. Each sampling capacitor set is coupled to an analog-signal input quantity through a sampling switch and to a corresponding output terminal of the sub DAC decoding circuit through a decoding switch. The sub DAC decoding circuit decodes a digital quantity and outputs a corresponding analog signal at each output terminal, such that the corresponding analog signals are applied to the respective sampling capacitor sets through the decoding switches and summed by the respective sampling capacitor sets to obtain an analog-signal quantity corresponding to the digital quantity.

Multiplying digital-to-analog converters and pipeline analog-to-digital converter using the same

A method for reducing a number of input terminals of an APC circuit is provided, where the APC circuit is arranged to control an optical pickup unit (OPU) within an optical storage device. The method includes: utilizing at least one switching module to ground one of a first and a second input terminals of the APC circuit at a time; and utilizing the switching module to electrically connect an APC front end within the APC circuit to a non-grounded input terminal of the first and the second input terminals, in order to receive a detection signal of a photo diode of the OPU through the non-grounded input terminal at the time. An associated APC circuit is also provided.

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Anhui, China

Cong Liu