Sun Microsystems, Inc.

Cong Fu

John D Davis

Manish K Shah

Ashley N Saulsbury

Jenn-Yuan Tsai

Greg F Grohoski

Venkatesh Iyengar

Jeff Gibson

A method and system for trace generation using memory index hashing. A method may include generating an extended trace representative of M threads of instruction execution from a trace representative of N threads of instruction execution, where N and M are integers, N&#x2267;1 and M&#x3e;N, and where each of the N threads of the trace includes memory references to respective memory addresses. Generating the extended trace from the trace may include replicating the N threads to generate the M threads, assigning a respective identifier to each of the M threads, and for a given one of the M threads, hashing a first portion of each of the respective addresses dependent upon the respective identifier of the given thread, where the first portion of each of the respective addresses corresponds to at least part of an index of a memory structure shared by at least two of the M threads.

Method and system for trace generation using memory index hashing

An apparatus and method for mapping memory addresses to reduce or avoid conflicting memory accesses in memory systems such as cache memories is described in connection with a multithreaded multiprocessor chip. A CMT processor reduces the probability of hot-spots in cache operations by hashing certain bits of a physical cache address to form a hashed cache address. By using exclusive OR functionality to hash the index bits, an efficient address transformation is achieved for indexing into an L2 cache memory.

Level 2 cache index hashing to avoid hot spots

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San Jose, CA, United States of America

Cong Fu