Altera Corporation

Intel Corporation

Colman Cheung

Dan Pritsker

Zhuan Ye

Benjamin Esposito

Steven Perry

Volker Mauer

James Tyson

Mark Jervis

Stephane Cauneau

Gregory Nash

Ray Schouten

An array of antennas includes transmitter and receiver circuits. The transmitter includes a digital-to-analog converter (DAC), splitter and filter circuits, mixer circuits, and antennas. The DAC circuit converts a digital signal into an analog signal. The splitter and filter circuits separate frequencies of the analog signal into split signals. The mixer circuits multiply frequencies from the split signals by different frequencies of carrier signals to generate modulated signals that are converted by the antennas into radio frequency (RF) signals. The receiver includes antennas, mixer circuits, a summing circuit, and an analog-to-digital converter (ADC). The antennas in the receiver receive RF signals that are converted into electrical signals. The mixer circuits multiply frequencies from the electrical signals with different frequencies of carrier signals. The outputs of the mixer circuits are summed by the summing circuit to generate a summed signal that is converted to digital by the ADC.

Systems and methods for electronically scanned array antennas

A circuit system includes an analog-to-digital converter circuit, a digital-to-analog converter circuit coupled to the analog-to-digital converter circuit, and a variable latency circuit coupled to a data path that includes the digital-to-analog converter circuit. The variable latency circuit generates a deterministic latency in an output signal that is based on a measured latency of the data path.

Analog-to-digital converter or digital-to-analog converter data path with deterministic latency

An oversampling channelizer for processing overlapping data that includes a data storage unit, coupled to a data line that receives data values. The data storage unit includes a plurality of lanes, wherein each of the plurality of lanes includes dedicated memory locations and wires that store and transmit data values for a data vector of a data frame, and that store and transmit additional data values for a subsequent data vector of a subsequent data frame that includes a plurality of the data values from the data vector in the data frame. The oversampling channelizer includes a coefficient storage unit that stores a plurality of coefficient vectors for a plurality of coefficient frames. The oversampling channelizer includes a computation unit that computes a dot product of the data values for the data vectors of the data frame with coefficient values for coefficient vectors of a coefficient frame selected by a coefficient storage unit.

Method and apparatus for implementing a super sample rate oversampling channelizer

Decimation filter circuitry may include polyphase filtering structures that perform decimation filtering using filter coefficients. Generic polyphase filtering structures do not take advantage of symmetries between the corresponding filter coefficients. If desired, the arrangement of the polyphase filtering structures in the decimation filter circuitry may be optimized relative to generic polyphase filtering structures to take advantage of corresponding filter coefficient symmetries, thereby allowing for implementation of dynamic decimation ratios and a dynamic number of channels while reducing the number of required multipliers by half with respect to generic polyphase filters. Decimation filters may include pre-adder circuitry that receives first and second portions of a data stream and adds corresponding samples from the first and second portions to generate pre-added values. Convolving circuitry may generate filtered output data by convolving the pre-added values with corresponding filter coefficients based on symmetry of the filter coefficients.

Dynamically adjustable decimation filter circuitry

Circuitry for interpolating a value based on a first plurality of samples from within a larger second plurality of samples includes storage for the second plurality of samples, including a plurality of sample memories corresponding in number to the first plurality of samples. Adjacent samples in the sample memories correspond to samples in the second plurality of samples that are separated by other samples numbering one less than that number. A first sample address into a first one of the sample memories is derived by dividing a floor of an index by the number. Respective circuitry for each respective other one of the sample memories derives a respective other sample address from the first sample address based on a remainder of dividing the floor of the index by the number. Shifting circuitry outputs selected samples in a second order under control of a value determined by the remainder.

Interpolation circuitry and methods

Techniques and mechanisms implement a sample rate converter for resampling data, such as audio data. The resampling may be based on a resampling clock. As the frequency of the resampling clock varies (e.g., due to jitter, rate adjustment, etc.), a control loop feedback mechanism can detect the variations and gradually correct the sampling rate of the resampled data.

Sample rate converter

One embodiment relates to an apparatus for sample rate conversion. A sample rate converter is arranged to receive an input signal at an input sampling frequency and use an interpolation interval to convert the input signal to an output signal at an output sampling frequency. A rate controller is arranged to alternate between different frequency control words for use in generating the interpolation interval signal. Another embodiment relates to a method of sample rate conversion. Another embodiment relates to a rate controller circuit. Other embodiments, aspects, and features are also disclosed.

Apparatus and methods of rate control for a sample rate converter

Efficient matrix operations circuitry is based on combining a matrix decomposition and a forward substitution operations to share the same processing overhead. A dual multiplier circuit selectively applies complex multiplication operations to a first and second input vectors for computing a conjugate dot product vector or a non-conjugate dot product vector. The conjugate dot product vector corresponds to the matrix decomposition operation for triangulating an input matrix to generate an element of a triangulated matrix. The non-conjugate dot product vector corresponds to a forward substitution operation for determining an element of a forward substitution vector from the triangulated matrix.

Matrix operations in an integrated circuit device

Methods, integrated circuits, and computer programs for managing a communication path carrying multiple channels are presented. Each channel includes a first-in first-out (FIFO) queue. In one method, the time difference between the start of a cycle for receiving data in a particular channel and a start of a cycle for transmitting data in the same particular channel is identified. Further, the method includes an operation for buffering arriving data in the communication path. The arriving data is buffered for an amount of time equal to the identified time difference, and the result is delayed data. FIFO registers are loaded from memory, which includes loading FIFO control and status data for a single FIFO queue, where the single FIFO queue is associated with the current channel of the produced delayed data at any time. Additionally, method includes an operation for processing contemporaneously read and write requests for the single FIFO queue using the loaded FIFO registers.

Shared control logic for multiple queues

Techniques for implementing multipliers using memory blocks in an integrated circuit (IC) are provided. The disclosed techniques may reduce the number of memory blocks required to implement various multiplication operations. A plurality of generated products is normalized. The normalized products are scaled to generate a plurality of scaled products. Scaled products with the least root mean square (RMS) error are identified. The scaled products with the least RMS error are then stored in a plurality of memory blocks in an IC. The scaled products may have a reduced number of bits compared to the plurality of generated products that have not been normalized and scaled.

Multipliers with a reduced number of memory blocks

Precise timing information produced by a block average module may be provided to signal processing circuitry. A sample period value generator may produce samples of the input data period values. A progressive block averaging computation may be applied to the generated input data period value samples. The output of the progressive block averaging computation may be used as the precise input sample rate information. The precise input sample rate information may in turn drive a signal processing application. The precision of the clock information may be increased with an increase in startup overhead.

Methods and apparatus for generating precise timing information using progressive block averaging

A receiving device oversamples incoming serial data using multiple phases of its system clock. The device detects an initial edge in the set of samples and selects a sample based on the location of the initial edge. A first bit is set to the value of the selected sample. A portion of the set of samples following the initial edge. If an edge is detected, then a sample is selected based upon the location of the detected edge and the next bit is set to the value of the selected sample. If an edge is not detected within this portion, then the position of the next edge is estimated. A sample is selected based upon the location of the estimated edge and the next bit is set to the value of the selected sample. The analysis is repeated for another portion of the set of samples following the newest edge.

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San Diego, CA, United States of America

Colman Cheung