Analog Devices,inc.

Mediatek Corporation

Colm J Prendergast

James M Wilson

Yosef Stein

Christopher Mayer

Joshua A Kablotsky

Edmund J Balboni

Daniel Boyko

Gregory M Yukna

Daniel E Fague

Thomas J Liptay

Timothy J Cummins

Brian Paul Murray

Olafur Mar Josefsson

Phillip M Sher

Philip A Curran

Sriram Krishnan

Jeffrey R Feigin

Richard P Schubert

Benoit Dufort

Matthew Aaron Hazel

Determining if a hermetically sealed MEMs device loses hermeticity during operation. In one embodiment, the MEMs device is an accelerometer. A test signal having an associated frequency above an operational frequency range for the accelerometer is provided to the accelerometer at an input during operation of the accelerometer for sensing an acceleration. The output signal of the accelerometer is filtered at least above the operational frequency range of the accelerometer producing a test output signal. The test output signal is then compared to a predetermined threshold to determine if the amplitude of the test output signal differs from the threshold. If the amplitude of the test output signal differs from the predetermined threshold, an error signal is produced indicating that hermeticity of the accelerometer has been lost.

System and method for run-time hermeticity detection of a capped MEMS device

Reducing pipeline stall between a compute unit and address unit in a processor can be accomplished by computing results in a compute unit in response to instructions of an algorithm; storing in a local random access memory array in a compute unit predetermined sets of functions, related to the computed results for predetermined sets of instructions of the algorithm; and providing within the compute unit direct mapping of computed results to related function.

Compute units using local luts to reduce pipeline stalls

A radio frequency (RF) receiver having an analog gain control section for controlling the gain of a received RF signal, and a digital demodulator section for demodulating the output of the gain control section, includes an analog GO circuit connected to recognize the presence of a data packet within a received RF signal in the analog gain control section, and in response to produce an analog GO signal, a digital GO circuit connected to recognize the presence of a data packet within the received RF signal from the digital demodulator section, and in response to produce a digital GO signal, and control circuitry connected to enable gain control functions within the analog gain control section and digital demodulator functions within the digital demodulator section in response to respective analog and digital GO signals.

Apparatus and method for RF packet detection and symbol timing recovery

Pipelined digital signal processor

Finite impulse response filtering is achieved by broadcasting to at least one compute unit an instruction having a plurality of data samples, a conditional field associated with each compute unit, and a set of operator values for operating on each data sample; providing a function of each the data sample in accordance with an associated set of operator values identified by the conditional field; and combining the functions to obtain an intermediate finite impulse response of the data samples.

Method and apparatus for accelerating processing of adaptive finite impulse response filtering

An RF receiver includes an analog GO circuit that recognizes the presence of a data packet within a received RF signal in the receiver's analog gain control section, and in response produces an analog GO signal, and a digital GO circuit that recognizes the presence of a data packet from the receiver's digital demodulator section, and in response produces a digital GO signal. Gain control functions within the analog gain control section, and digital demodulator functions within the digital demodulator section, are enabled in response to respective analog and digital GO signals. The system is capable of distinguishing a valid data packet from noise, co-channel interference and adjacent panel interference. A symbol timing recovery circuit within the receiver identifies periodic samples of a data packet preamble that most closely match the preamble bits, with the receiver employing a continuation of the identified periodic samples to decode the remainder of the data packet.

A calibration system for a communication system is provided featuring a transmitter circuit, a receiver circuit, a transmission medium having a transfer function for transmitting a signal between the transmitter and receiver circuits, and a calibration system responsive to the altered reference signal of the transmitter circuit for adjusting the reference signal level of one of the transmitter and receiver circuits to compensate for variations in the transmission signal due to the transfer function.

Calibration system for a communications system

Frequency offsets between a received carrier signal and a receiver's LO frequency are compensated by determining the offset and adjusting the phase of a demodulated signal derived from the modulated carrier. For frequency offsets that produce DC voltage offsets in I and Q components of the demodulated signal, the phase correction is implemented by operating upon the I and Q components with phase rotation operators in the form of sin &#x3b8; and cos &#x3b8;, where &#x3b8; is an angle whose tangent is the result of dividing the Q by the I frequency offsets.

Method and apparatus for frequency offset compensation

An isolation system with analog communication across an isolation barrier includes an isolation barrier circuit having at least one isolation element; a digital to analog circuit having an analog output connected to the isolation barrier and an input for receiving an input digital signal to be communicated across the isolation barrier; and an analog to digital circuit having an input coupled to the analog output of the isolation barrier circuit for providing a digital output signal.

Isolation system with analog communication across an isolation barrier

A device comprises a termination impedance circuit, coupled to a communication link. The termination impedance circuit provides a termination impedance of the device, wherein the impedance is selectable. A second device comprises an echo-cancel hybrid circuit, coupled to a communication link, that provides an echo cancel characteristic, wherein the characteristic is selectable.

Configurable analog front end for communication systems

A first device receives and processes signals from a communication link that supports a plurality of signal protocols. The device comprises a converter, coupled to the communication link, that outputs a sampled data stream, and a digital filter that filters the sampled data stream to separate signals associated with different signal protocols. A second device receives a first input sampled data stream representative of a first signal to be transmitted and associated with a first signal protocol and a second input sampled data stream representative of a second signal to be transmitted and associated with a second signal protocol, and combines the data streams into an output data stream which may be coupled to the communication link.

Device for use in communication systems

A first device comprises a loop circuit to control a sample rate of a digital circuit element. A circuit comprises a digital loop circuit to control a sample rate of a digital circuit element to be a function of a frequency of a signal received by the circuit. A second device receives two or more sampled data streams having sample rates different from one another, converts the sample rate of one or more of the data streams to provide two or more data streams having sample rates compatible with one another, and combines the two data streams. Sample rate converter devices are used in a PLL and a clock recovery circuit.

Device for use in controlling a sample rate

A digital-to-analog video encoder method and apparatus having unique equalization are disclosed. The encoder converts digital video signals into one or more analog video formats using one or more digital-to-analog converters. Equalization is provided to compensate for zero order hold effects of the digital-to-analog converters. Equalization is provided to a luminance signal and/or a chroma signal to equalize RGB, composite video, and super VHS video outputs. Multiplexed digital-to-analog converter inputs allow selection of several output formats.

Digital-to-analog video encoder with novel equalization

A novel finite impulse response filter apparatus and method. A multiplexed data stream composed of two or more data streams is provided as an input to a tapped delay line. Weight and sum operators are connected to the even or odd delay line taps and generate a filtered output. The filter operates on one data stream per cycle and generates a multiplexed output. In another form, odd weight and sum operates are connected to and odd taps generating two filtered outputs. The filter operates on both data streams in each cycle and generates two multiplexed outputs. A crossbar switch is disclosed for parsing the multiplexed outputs into the constituent filtered data streams. The filter stages may be cascaded.

Growing community of inventors

Cambridge, MA, United States of America

Colm J Prendergast