Hrl Laboratories, LLC

The Boeing Company

Colleen M Butler

Miroslav Micovic

Keisuke Shinohara

Dean C Regan

David T Chang

Alexandros Margomenos

Andrea Corrion

Ivan Milosavljevic

Peter J Willadsen

Hector L Bracamontes

Bruce T Holden

Hasan Sharifi

Ara K Kurdoghlian

A semiconductor device comprises one or more transistors and two or more layers of dielectric material encapsulating a front side of said one or more transistors. The gate of each of said one or more transistors is located within a cavity, or air-box, in at least one of the dielectric layers, so that the gate terminal is physically separated from said dielectric material. Such an arrangement may reduce parasitic capacitance. In another arrangement, a semiconductor device comprises one or more gallium nitride high electron mobility transistors and one or more dielectric layers encapsulating a front side of said one or more transistors, wherein the gate terminal of each of said one or more transistors is located within a cavity in at least one of the one or more dielectric layers, separated from said dielectric material.

Method and structure for encapsulation and interconnection of transistors

A method for fabricating a gate structure for a field effect transistor having a buffer layer on a substrate, a channel layer and a barrier layer over the channel layer includes forming a gate of a first dielectric, forming first sidewalls of a second dielectric on either side and adjacent to the gate, selectively etching into the buffer layer to form a mesa for the field effect transistor, depositing a dielectric layer over the mesa, planarizing the dielectric layer over the mesa to form a planarized surface such that a top of the gate, tops of the first sidewalls, and a top of the dielectric layer over the mesa are on the same planarized surface, depositing metal on the planzarized surface, annealing to form the gate into a metal silicided gate, and etching to remove excess non-silicided metal.

Gate metallization methods for self-aligned sidewall gate GaN HEMT

A method of integrating benzocyclobutene (BCB) layers with a substrate is provided along with a corresponding device. A method includes forming a first BCB layer on the substrate and depositing a first metal layer on the first BCB layer and within vias defined by the first metal layer. The method also forms a second BCB layer on the first metal layer and deposits a second metal layer on the second BCB layer and within vias defined by the second metal layer. The second metal layer extends through the vias defined by the second metal layer to establish an operable connection with the first metal layer. The first and second metal layers are independent of an electrical connection to any circuit element carried by the substrate, but the first and second metal layers secure the second BCB layer to the underlying structure and reduce the likelihood of delamination.

Method of integrating a plurality of benzocyclobutene layers with a substrate and an associated device

A method for fabricating a gate structure for a field effect transistor having a buffer layer on a substrate, a channel layer and a barrier layer over the channel layer includes forming a gate including silicon, forming first sidewalls of a first material on either side and adjacent to the gate, selectively etching into the buffer layer to form a mesa for the field effect transistor, depositing a material layer over the mesa, planarizing the material layer over the mesa to form a planarized surface such that a top of the gate, tops of the first sidewalls, and a top of the material layer over the mesa are on the same planarized surface, depositing metal on the planzarized surface, annealing to form the gate into a metal silicided gate, and etching to remove excess non-silicided metal.

Growing community of inventors

Camarillo, CA, United States of America

Colleen M Butler