Advanced Micro Devices Corporation

Spansion Llc.

Synopsys, Inc.

Other

Fujitsu Corporation

Kilopass Technology, Inc.

Cypress Semiconductor Corporation

Colin Stewart Bill

Ravi Prakash Gutala

Tzu-Ning Fang

Jonathan S Su

Sameer S Haddad

Michael A VanBuskirk

Edward V Bautista, Jr

Zhida Lan

Wei Daisy Cai

Feng Q Pan

Takao Akaogi

Michael Allen Van Buskirk

Swaroop Kaza

Ravi S Sunkavalli

Shigekazu Yamada

Ken Cheong Cheah

David Gaun

Wing Han Leung

John Chen

Harry Luan

Vei-Han Chan

Michael Vanbuskirk

Azrul Halim

Jonathan Shi-Chang Su

Darlene G Hamilton

Eugen Gershon

Youseok Suh

Ya-Fen Lin

Stuart Spitzer

Weng Fook Lee

Yi-Ching Jean Wu

Vei-Han Chen

Matthew S Buynoski

Steven C Avanzino

Suzette Keefe Pangrle

Pau-Ling Chen

Binh Quang Le

Nicholas H Tripsas

Shane Charles Hollmer

Antonio J Montalvo

Richard Paul Kingsborough

Juri Krieger

An Chen

Igor Sokolik

Michael Van Buskirk

Mark Alan McClain

Santosh K Yachareni

Chung-You Hu

Boon Tang Teh

Joseph Kucera

Syahrizal Salleh

Weng F Lee

Shigekasu Yamada

Jean Wu

Qimeng (Derek) Zhou

John S Ennals

Qimeng Derek Zhou

A physical unclonable function (PUF) circuit generates one or more bit values. The PUF circuit includes a first one-time programmable (OTP) memory cell, a second OTP memory cell, and a latch circuit connected to the first and second OTP memory cells. The latch circuit initiates programming of the first and second OTP memory cells, detects a faster programming OTP memory cell of the first and second OTP memory cells, inhibits programming of a slower programming OTP memory cell of the first and second OTP memory cells, and stores a first bit value when the first OTP memory cell is the faster programming OTP memory cell and a second bit value when the second OTP memory cell is the faster programming OTP memory cell.

PUF latch for OTP memory arrays and method of operation

An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.

MTP-Thyristor memory cell circuits and methods of operation

A protection circuit for an integrated circuit product die or die-let (die-let) is responsive to whether the die-let has undergone a dicing operation or not. A test circuit on the die-let's semiconductor wafer can test and/or configure the die-let. After the dicing operation, the protection circuit generates a signal to isolate the cut input lines from the test circuit to prevent any interference with the normal operation of the integrated circuit product die-let.

Protection circuit for integrated circuit die-let after scribe cut

A low power voltage level shifter circuit in which current is limited through at least one of a plurality of CMOS logic circuits, one of which receives input signals within a first voltage level and is connected between a first upper and lower power supply, a second of which transmits shifted output signals within a second voltage level and is connected between a second upper and lower power supply. There is at least one current-limiting MOS transistor connected between at one of the CMOS logic circuits and one of its power supplies. Typically, there is at least one current-limiting MOS transistor between the second CMOS logic circuit which transmits the shifted output signals which have a larger range than that of the input signals. A second current through the at least one current-limiting MOS transistor mirrors a set current through a first MOS transistor so that power consumed by the CMOS logic circuit during switching is limited.

Low power voltage level shifter circuit

MTP-thyristor memory cell circuits and methods of operation

A low power consuming read circuit for a memory array is disclosed. The circuit is particularly useful in applications where oxide breakdown one-time programmable memory is integrated into a system having low power available from the power sources supplying the system.

Reduced power read sensing for one-time programmable memories

A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word lines adjacent to the selected word line, improve self boost efficiency and reduce current leakage to prevent or reduce program disturb and/or programming errors especially in the inhibited memory cells on the selected word line.

Partial local self boosting for NAND

A write-once read-many times memory device is made up of first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrode. The memory device is programmed by providing a charged species from the passive layer into the active layer. The memory device may be programmed to have for the programmed memory device a first erase activation energy. The present method provides for the programmed memory device a second erase activation energy greater than the first erase activation energy.

Method of providing an erase activation energy of a memory device

In a first method of writing data to a resistive memory device (i.e. programming or erasing), successive electrical potentials are applied across the resistive memory device, wherein the successive electrical potentials are of increasing duration. In another method of writing data to a resistive memory device (i.e. programming or erasing), an electrical potential is applied across the resistive memory device, and the level of current through the memory device is sensed as the electrical potential is applied. The application of the electrical potential is ended based on a selected level of current through the resistive memory device.

Methods of programming and erasing resistive memory devices

The present disclosure adjusts the voltage threshold values of select gates of NAND strings. The select gates of the NAND string can be read, erased, and programmed.

Non-volatile memory device and methods of using

A memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes is disclosed. The controllably conductive media includes a passive layer made of super ionic material and an active layer. When an external stimuli, such as an applied electric field, is imposed upon the first and second electrode, ions move and dope and/or de-dope the polymer. The applied external stimuli used to dope the polymer is larger than an applied external stimuli to operate the memory cell. The polymer functions as a variable breakdown characteristic diode with electrical characteristics which are a consequence of the doping degree. The memory element may have a current limited read signal. Methods of making the memory devices/cells, methods of using the memory devices/cells, and devices such as computers, hand-held electronic devices and memory devices containing the memory cell(s) are also disclosed.

Variable breakdown characteristic diode

A metal sulfide based non-volatile memory device is provided herein. The device is comprised of a substrate, a backplane, a planar memory media including a dense array of metal sulfide based memory cells, and a MEMS probe based actuator. The cells of the memory device are operative to be of two or more states corresponding to various levels of impedance. The MEMS actuator is operable to position micro/nano probes over the appropriate cells to enable reading, writing, and erasing the memory cells by applying a bias voltage.

Using organic semiconductor memory in conjunction with a MEMS actuator for an ultra high density memory

Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.

Use of periodic refresh in medium retention memory arrays

Growing community of inventors

Cupertino, CA, United States of America

Colin Stewart Bill