Raytheon Company

Colin Steven Whelan

Philbert Francis Marsh

Matthew D Thoren

Andrew M Piper

Joseph C DiMare

William E Hoke

Matthew A Morton

Francois Y Colomb

Robert E Leoni

Elsa K Tong

Barry J Liles

Matthew C Tyhach

John C Tremblay

Benjamin L Caplan

Steven G Labitt

Charles L Holland

Eugene Lee

Traugott Carl Ludwig Gerhard Soliner

Raghu Mallavarpu

Matthew Tynach

Radar systems and methods detecting and tracking an unmanned aerial system (UAS) are provided. The radar system and methods can include determining whether or not a UAS is included in the plurality of electromagnetic signals received by the radar system based on one or more expected frequencies that one or more UAS devices use to transmit signals to remote controls. The radar systems and method can also involve switching the radar system into a track mode upon detecting a UAS.

Systems and methods for detection and tracking of unmanned aerial systems

A system includes a UV light source and an optical medium coupled to receive UV light from the UV light source. The optical medium is configured to emit UV light proximate to a surface from which biofouling is to be removed once the biofouling has adhered to the protected surface. A method corresponds to the system.

Method and apparatus for removing biofouling from a protected surface in a liquid environment

A selective frequency limiter having a magnetic material and a slow wave structure disposed to magnetically couple a magnetic field, produced by electromagnetic energy propagating through the slow wave structure, into the magnetic material.

Frequency selective limiter

A method and structure for reducing cracks in a dielectric in contact with a metal structure. The metal structure comprises a first metal layer; a second metal layer disposed on, and in contact with the first metal layer, the second metal layer being stiffer than the first metal layer; a third metal layer disposed on, and in contact with the second metal layer, the second metal layer being stiffer than the third metal layer. An additional metal is included wherein the dielectric layer is disposed between the metal structure and the additional metal.

Method and structure for reducing cracks in a dielectric layer in contact with metal

A circuit having: an input matching network; a transistor coupled to an output of the input matching network; and wherein the input matching network has a first input impedance when such input matching network is fed with an input signal having a relatively low power level and wherein the input matching network has an input impedance different from the first input impedance when such input matching network is fed with an input signal having a relatively high power level.

Input circuitry for transistor power amplifier and method for designing such circuitry

Method for designing input circuitry for transistor power amplifier

A method for passivating a photodiode so as to reduce dark current, I, due to the exposed semiconductor material on the sidewall of the device. The method includes etching away sidewall surface damage using a succinic acid-hydrogen peroxide based sidewall etch. This is followed by a subsequent hydrochloric acid (HCl)-based surface treatment which completes the surface treatment and reduces the dark current I. Finally, a polymer coating of benzocyclobutene (BCB) is applied after the surface treatment to stabilize the surface and prevent oxidation and contamination which would otherwise raise the dark current were the diodes left with no coating. The BCB is then etched away from the contact pad areas to allow wirebonding and other forms of electrical contact to the diodes. Such method effectively stabilizes the etched surfaces of photodiodes resulting in significantly reduced and stable dark current.

Photodiode passivation technique

A method for passivating a III-V material Schottky layer of a field effect transistor. The transistor has a gate electrode in Schottky contact with a gate electrode contact region of the Schottky layer. The gate electrode is adapted to control a flow of carriers between a source electrode of the transistor and a drain electrode of such tarnsistor. The transistor has exposed surface portions of the Schottky layer beween the source electrode and the drain electrode adjacent to the gate electrode contact region of the Schottky layer. The method includes removing organic contamination from the exposed surface portions of the Schottky layer using a oxygen plasma. The contamination removed surface portions of the Schottky layer are exposed to a solution of ammonium sulfide and NHOH. After removal of the solution, the exposed regions are dried in a nitrogen enviroment. A layer of passivating material is deposited over the dried surface portions.

Sulfide encapsulation passivation technique

A method is provided for forming a self-aligned, selectively etched, double recess high electron mobility transistor. The method includes providing a semiconductor structure having a III-V substrate; a first relatively wide band gap layer, a channel layer, a second relatively wide band gap Schottky layer, an etch stop layer; a III-V third wide band gap layer on etch stop layer; and an ohmic contact layer on the third relatively wide band gap layer. A mask is provided having a gate contact aperture to expose a gate region of the ohmic contact layer. A first wet chemical etch is brought into contact with portions of the ohmic contact layer exposed by the gate contact aperture. The first wet chemical selectively removes exposed portions of the ohmic contact layer and underlying portions of the third relatively wide band gap layer. The etch stop layer inhibits the first wet chemical etch from removing portions of such etch stop layer. Next, a second wet chemical etch is brought into contact with structure etched by the first wet chemical etch. The second wet chemical etch selectively removes exposed portions of the ohmic contact layer while leaving substantially un-etched exposed portions of the third relatively wide band gap layer, the Schottky contact layer and the etch stop layer. The etch stop layer is removed. A metal layer is deposited over the mask and through gate aperture therein onto, and in Schottky contact with, the Schottky contact layer.

Method of forming a self-aligned, selectively etched, double recess high electron mobility transistor

A transistor structure having an gallium arsenide (GaAs) semiconductor substrate; a lattice match layer; an indium aluminum arsenide (InAlAs) barrier layer disposed over the lattice match layer; an In Ga As lower channel layer disposed on the barrier layer, where y is the mole fraction of In content in the lower channel layer; an In Ga As upper channel layer disposed on the lower channel layer, where x is the mole fraction of In content in the upper channel layer and where x is different from y; and an InAlAs Schottky layer on the In Ga As upper channel layer. The lower channel layer has a bandgap greater that the bandgap of the upper channel layer. The lower channel layer has a bulk electron mobility lower than the bulk electron mobility of the upper channel layer where.

Growing community of inventors

Wakefield, MA, United States of America

Colin Steven Whelan