International Computers Limited

Xyratex Technology Limited

Colin Martin Duxbury

Philip V Rose

Raymond Yates

John Richard Eaton

Ian David Johnson

Marek Stephen Piekarskl

A data switching device has ingress routers and egress routers interconnected by a switching matrix controlled by a controller. Each ingress router maintains one or more virtual output queues for each egress router. The switching matrix itself maintains a head-of queue buffer of cells which are to be transmitted. Each of these queues corresponds to one of the virtual output queues, and the cells stored in the switching matrix are replicated from the cells queuing in the respective virtual output queues. Thus, when it is determined that a connection is to be made between a given input and output of the switching matrix, a cell suitable for transmission along that connection is already available to the switching matrix. Upon receipt of a new cell by one of the ingress routers, the cell is stored in one of the virtual output queues of the ingress router corresponding to the egress router for the cell, and also written the corresponding head of queue buffer, if that buffer has space. If not, the cell is stored, and written to the head of queue buffer when that buffer has space for it.

Switching system

Data processing apparatus comprises a series of pipeline units each of which consists of a number of pipeline stages. The units are interconnected by a number of parameter files, which provide a number of slots. Whenever an instruction is initiated in the pipeline, it is allocated a slot, and retains that slot until its execution is successfully completed. Two independent streams of instructions are scheduled through the pipeline, each being allocated a fixed number of the slots. In normal operation, one of the streams has priority over the other stream. An instruction is allowed to change the process state only when it successfully terminates at the end of the pipeline, thus ensuring consistency. An instruction can be started in a lower pipeline unit as soon as it is know that its required operand will be available in time from the data slave, thus allowing the operations of these two units to be overlapped.

Pipelined data processor with parameter files for passing parameters

A pipelined data processing system comprises a series of pipeline stages through which instructions pass sequentially. If an error associated with a particular instruction (e.g. an illegal instruction) is detected, a Mayday signal is produced. This does not become active immediately. Instead it is passed down the pipeline along with the instruction that caused it, and becomes active only if that instruction attempts to terminate at the end of the pipeline. When the Mayday becomes active, it causes an interrupt to a diagnostic processor. If, on the other hand, the instruction that caused the Mayday is aborted, or does not attempt to terminate, then the Mayday is discarded and does not become active. This prevents unnecessary diagnostic actions.

Apparatus and method for detecting errors in a pipeline data processor

In a pipelined data processor, when a dependency is detected between a first instruction and a second, subsequent instruction, the second instruction is abandoned. A look-ahead mode of operation is then initiated, in which instructions subsequent to the abandoned instruction are allowed to continue to be executed so as to pre-fetch operands, but are not allowed to be fully executed. The processor has two separate streams of instructions, each of which streams can be independently put into look-ahead mode. When one stream is in look-ahead mode, the other is given priority.

Pipelined processor with look-ahead mode of operation

Data transmission apparatus is described in which data is transmitted over a communication link consisting of a bundle of optical fibres. Each message is transmitted as a sequence of groups of data bits, the bits in each group being transmitted in parallel over the fibres. Each fibre carries a signal encoded by a self-clocking code, and each message is preceded by a serial start pattern on each fibre. The receiver (311) comprises a plurality of decoders (520-524) for extracting separate clock and data signals from each fibre. These signals are fed to separate start pattern detection circuits (570-574). When a start pattern has been detected on all the fibres, the message data is clocked from each fibre into a separate buffer. The contents of the buffers are then read out in parallel. The arrangement overcomes the problems of data skew due to different transmission times over the fibres.

Parallel optical data transmission system

A multi-node data processing system is described in which each node (10-13) includes a processor (PROC) and an inter-node switch (INS). In operation, only one INS is active. The active INS is configured to act as a star coupler, receiving messages from any of the nodes and broadcasting each message to all the nodes including the node in which that INS is located. Each non-active INS is configured to route messages from the local processor to the active INS, and to route incoming messages broadcast by the active INS to the local processor. The system can be reconfigured to make a different INS active.

Multi-node data processing system

A data transmission system is described, comprising a plurality of processing nodes (10-13). At any given time, one of the nodes acts as a star coupler, for broadcasting messages to all the other nodes. This node uses a plurality of counters (361-363) to keep track of the amount of available space in the receive buffers (351) of the other nodes. Whenever a message is broadcast, all the counters are decremented. Conversely, whenever an acknowledgement signal is received, indicating that one of the other nodes has removed a message from its buffer, the corresponding counter is incremented. If any of the counters indicates that a buffer is full or nearly full, broadcasting is suspended. If any of the nodes develops a fault, preventing it from removing messages from its buffer, it transmits a constant stream of acknowledgement signals, thereby preventing the corresponding counter from indicating 'full' and hence allowing the system to continue running.

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Woodley, United Kingdom

Colin Martin Duxbury