Freescale Semiconductor,inc.

Nxp Usa, Inc.

Motorola Corporation

Colin MacDonald

Anis Mahmoud Jarrar

Alexander Hoefler

Jose A Lyon

Alan Joseph Carlin

Andrew H Payne

John M Dalbey

Chris C Dao

Donald L Tietjen

David Russell Tipple

Simon Gallimore

James H Carlquist

Kristen L Mason

Chris P Nappi

Tamas Kovacs

A FinFet capacitor structure includes a first, second, third, and fourth FinFet fin, a contiguous gate layer over the fins, first and second source/drain contacts in direct physical contact with the first FinFet fin on either side of the gate layer, a first gate contact in direct physical contact with a portion of the contiguous gate layer directly over the second FinFet fin, third and fourth source/drain contacts in direct physical contact with the third FinFet fin on either side of the gate layer, and a second gate contact in direct physical contact with a portion of the contiguous gate layer directly over the fourth FinFet fin. The first, second, third, and fourth source/drain contacts are all connected to a first power supply rail, and the first and second gate contacts are all connected to a second power supply rail.

Fin field-effect transistor (FinFet) capacitor structure for use in integrated circuits

A scan circuit and methods of operating a scan circuit are provided. The method for operating a scan circuit includes providing a first scan flip-flop which includes an overwrite feature. With the overwrite feature enabled, a change in functional behavior of the first scan flip-flop occurs based on a control signal. The method may further include capturing data at a first input of the first scan flip-flop during a first state of the control signal and resetting captured data by using the overwrite feature during a first transition of the control signal. The method may further include forming a scan chain with one or more of the first scan flip-flops and one or more second scan flip-flops. The second scan flip-flops may include a similar overwrite feature, having the overwrite feature disabled.

Data processing system with built-in self-test and method therefor

An integrated circuit includes a plurality of state retention power gating (SRPG) flip-flops coupled in a first chain, wherein the first chain has a first scan input and a first scan output; a pseudo random pattern generator (PRPG) configured to generate test patterns in response to seeds; a multiplexer (MUX) coupled between the PRPG and the first scan input and coupled to receive a select signal; and response compression logic coupled to the first scan output and configured to generate a test signature in response to an output pattern provided at the first scan output. The MUX is configured to, when the select signal has a first value, couple a first output of the PRPG to the first scan input, and, when the select signal has a second value, couple an inversion of the first output of the PRPG to the first scan input.

Circuit and method for testing flip flop state retention

An integrated circuit device includes a peripheral control circuit configured to receive a low power intent signal from a first processor, and a first control register in the peripheral control circuit. The first control register includes a peripheral enable indicator for each processor that can use a first peripheral. Acknowledgement logic circuitry is configured to assert a first low power acknowledgement signal when the first processor issuing the low power intent signal has enabled use of the first peripheral as indicated by the peripheral enable indicator for the first processor in the first control register.

Multiprocessing system with peripheral power consumption control

A data processing system includes first and second power distribution networks to provide power at first and second voltages, and a flip-flop. The second voltage is less than the first voltage. The flip-flop includes a master latch with a power node connected to the first power distribution network, a data signal input, and an output signal output that is driven at the first voltage, and a slave latch with a power node connected to the first power distribution network, an input coupled to the output of the master latch, a slave latch output signal output that is driven by the first voltage, and a feedback circuit with a first latch inverter having a power node connected to the second voltage, an input coupled to the master latch output, and an output terminal to provide an output signal that is driven by the second voltage.

Low swing flip-flop with reduced leakage slave latch

This disclosure describes a multi-height routing cell and utilization of the multi-height routing in an integrated circuit to reduce routing congestion in a standard cell design floorplan. The multi-height routing cell includes a bypass connection, or 'tunnel,' that routes a signal through a non-routing layer and under an impeding power rail. The multi-height routing cell includes bypass connectors on both sides of the bypass connection that provide connection points for which to connect standard cells on opposite sides of the impeding power rail. As such, the multi-height routing cell provides a route underneath the impeding power rail and, in turn, reducing routing congestion in the standard cell design floorplan.

Routing standard cell-based integrated circuits

A method includes determining a first operational characteristic representative of an operational speed of a circuit device at a first time. The method further includes receiving an input signal at an input of a first latch of the circuit device and receiving an output signal at an input of a second latch of the circuit device. The method additionally includes delaying a clock signal by a first delay to provide a first adjusted clock signal and delaying the clock signal by a second delay to provide a second adjusted clock signal. In one embodiment, the first delay and the second delay are based on the first operational characteristic. The method further includes latching the input signal at the first latch responsive to the first adjusted clock signal and latching the output signal at the second latch responsive to the second adjusted clock signal.

Dynamic timing adjustment in a circuit device

An integrated circuit is configured with a pin for specifying a reset configuration vector of a circuitry within the integrated circuit. The resistance value of a low cost external resistor coupled to the pin is detected and utilized to identify the configuration. Logic on the integrated circuit detects and utilizes the resistor value to index to a configuration vector in a look-up table. The integrated circuit is then configured in accordance with the indexed configuration vector.

Low pin count reset configuration

A system an method of designing an integrated circuit identifies a plurality of synchronous cells of an integrated circuit to be driven by a clock driver, wherein the plurality of synchronous cells are a subset of previously placed cells of the integrated circuit. The placement of synchronous cells is performed to reduce a current needed from the clock driver to drive the plurality of synchronous cells.

System and method for reducing the power consumption of clock systems

A method and system for transmitting binary-coded data use partitioning of data words in a plurality of data nibbles. The data nibbles are coded using modified a 1-bit hot coding format that transforms a data nibble in a data segment including a plurality of bit groups. A change in a digital state at a bit position in a more significant bit group is maintained at that bit position in less significant bit groups, and information is transmitted in a form of a transition between digital states. The data segments are transmitted in phases each including one bit group from each data segment. At a receiving terminal, the bit groups are converted back in the binary-coded data words. In one application, the invention is used to reduce power consumption during data transmissions to and from an integrated circuit device.

Method and system for transmitting data

Embodiments of the present invention relate to deterministic prediction in an image processing system. One aspect relates to an image processing system having a deterministic prediction decode unit for predicting individual pixels of an image based on a predetermined deterministic prediction algorithm. The deterministic prediction decode unit includes a look-up table, organized into four spatial phases, for storing values to be used by the predetermined deterministic prediction algorithm when converting a relatively low resolution image to a relatively higher resolution image. A prediction is made for a target pixel by accessing at least two of the four spatial phases of the look-up table to read at least two possible values of the target pixel. In one embodiment, the value of two target pixels can be provided within a same clock period, thus allowing for the decoding of two spatial phases with each access to the look-up table.

Deterministic prediction in an image processing system

A circuit for processing a first image including two image supply blocks, two image processing units, a control unit and a plurality of buses. The image supply blocks assert selected lines of image data onto a respective one of first and second plurality of buses. The image processing units each process the data according to respective algorithms and provide respective update ok signals that each indicate that the respective image processing unit has completed use of the first sub-portion of data. The image supply blocks provide respective update signals to the image processing units in response to the update ok signals from both of the image processing units, transfer data from the second sub-portion to the first, and assert new data on the second sub-portion. Each image processing unit, in response to receiving both update signals, changes state to track the data without losing bus cycles to maintain performance.

Image processing system with multiple processing units

A memory controller (,) compares the current address and the previous address sent by a microprocessor (,). If the addresses are DRAM addresses and the current row address matches the previous row address, i.e. same DRAM page access, then the memory controller disables caching (,) of the same DRAM page access. The same DRAM page access disables caching because the same DRAM page access is not substantially longer than a cache access. A counter (,) and comparator (,) allows the memory controller to hold off some number of same DRAM page accesses before disabling caching to give time for the memory controller to set up to the new page.

Growing community of inventors

Austin, TX, United States of America

Colin MacDonald