Qinetiq Limited

Colin John Hollier

Neil Thomson Gordon

Jean Giess

Graham J Pryce

Janet E Hails

Andrew Graham

Louise Buckle

John W Cairns

David J Hall

Andrew J Wright

A random access decoder comprising a plurality of decoder circuit elements, each decoder circuit element having a unique electronic address and a binary data output, means for applying an input signal to each of the decoder circuit element and where each decoder circuit element places data on its binary data output only when the unique electronic address of a particular decoder circuit element matches the applied input signal and wherein the unique electronic address of each of the plurality of decoder circuit elements is electronically loaded into each of the decoder circuit elements. In one embodiment, each decoder circuit element comprises equivalent components electrically connected in the same arrangement.

Random access decoder

This invention relates to the manufacture of Cadmium Mercury Telluride (CMT) on patterned silicon, especially to growth of CMT on silicon substrates bearing integrated circuitry. The method of the invention involves growing CMT in selected growth windows on the silicon substrate by first growing one or more buffer layers by MBE and then growing the CMT by MOVPE. The growth windows may be defined by masking the area outside of the growth windows. Growth within the growth windows is crystalline whereas any growth outside the growth windows is polycrystalline and can be removed by etching. The invention offers a method of growing CMT structures directly on integrated circuits removing the need for hybridisation.

Manufacture of cadmium mercury telluride on patterned silicon

A random access decoder () comprising a plurality of decoder circuit elements (), each decoder circuit element having a unique electronic address and a binary data output (), means for applying an input signal () to each of the decoder circuit element and where each decoder circuit element places data on its binary data output () only when the unique electronic address of a particular decoder circuit element () matches the applied input signal () and wherein the unique electronic address of each of the plurality of decoder circuit elements () is electronically loaded into each of the decoder circuit elements (). In one embodiment, each decoder circuit element () comprises equivalent components electrically connected in the same arrangement.

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Malvern, United Kingdom

Colin John Hollier