Mitsubishi Denki Kabushiki Kaisha

Apricot Computers Limited

Colin Hough

Kunio Takahari

Toshikazu Yokoi

Nigel Bruce

Yoichi Nakamura

Masahiro Ishii

David P Wright

Atsushi Toshima

Satoshi Kobayashi

Junichi Ishikawa

There is provided with an information processing system capable of updating a basic input/output system (BIOS) programme without interrupting or stopping the operation of the system. The information processing system (41) comprises an update programme memory (48) and a BIOS update flag (50). The update programme memory (48) retains the contents stored therein after the electrical power to the information processing system (41) has been turned off. An update programme input arrangement supplies an update basic input/output system programme to the update programme memory (48) to write the programme thereinto while the operating system is in operation. The update programme input arrangement then sets the BIOS update flag (50). A system loading arrangement copies the update basic input/output system programme stored in the update programme memory (48) to a memory area of a main memory (44) when the BIOS update flag (50) is set upon loading the operating system (i.e., when the information processing system is turned on or is reset).

Information processing system capable of updating a BIOS programme

A symmetric multiprocessor system connecting a plurality of CPUs by a common bus initializes itself while defective CPUs are set aside to use only the remaining CPUs when the power is turned on, thereby maintaining the predetermined CPU numbers and giving a minimum influence with the existing software thereof. The multiprocessor system includes an identifier setting register to designate in a predetermined order the CPU numbers only to normal CPUs, and a reset controller to cut off the defective CPUs from the common bus. The multiprocessor system can automatically start re-setting up where the defective CPUs are detected during the processing of setting-up based on the time-out detection, can release an abnormal state of the hardware, and can control the setting-up processing in use of any CPU based on the level of a reset status input port and contents of a reset information register.

Method and apparatus for initializing a multiprocessor system while

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Birmingham, United Kingdom

Colin Hough