Analog Devices,inc.

Analogic Corporation

Analog Devices Global

Colin Charles Price

Michael Byrne

Michael C W Coln

Jeremy Richard Gorbold

Derek J Hummerston

Nicola M O'Byrne

Colin S McIntosh

Christopher Peter Hurrell

Mahesh Madhavan Kumbaranthodiyil

Christian Steffen Birk

John R Reidy

Asif Ahmad

Gerard Mora Puchalt

John Blake

Steven Boyle

Simon Smith

Mark Stephen Power

Anthony Gribben

An analog multiplexer may be used for sampling an input voltage that is capable of having a higher voltage level than an upper supply voltage. The analog multiplexer includes a plurality of input switch circuits and a shorting switch circuit. The plurality of input switch circuits include n-type or p-type laterally diffused field effect transistors (NLDFETs or PLDFETs). At least one of the input switch circuits includes a level shifting switch circuit that is able to sample an input voltage that is greater than the upper supply voltage for the multiplexer. A shorting switch circuit, at an output of the multiplexer, includes a capacitively coupled gate drive circuit and is configured to short a first differential output to a second differential output after the input voltage is sampled.

Analog multiplexer

Embodiments of the present invention provide a monitoring system that may include a plurality of monitors. Each may have a plurality of input pairs coupled to respective components of a component stack, wherein adjacent monitors each have an input pair coupled to a common component. Embodiments of the present invention provide an integrated circuit that may include a plurality of detectors to locally measure a first group of channels. The integrated circuit may also include a receiver operable to receive a measurement of at least one channel of the first group of channels, and a controller to calculate a correction factor based on the received measurement and a local measurement of the at least one channel and to correct all first group measurements with the correction factor.

Accuracy of battery monitor parts

A measuring apparatus including a self test function, the circuit comprising a capacitor; first to fourth switches; a test signal injector; at least one comparator having a signal input and a reference input the first switch being interposed between a first plate of the capacitor and a first input node, the second switch being interposed between a second plate of the capacitor and a second input node, the third switch being interposed between the first plate of the capacitor and the signal input of the comparator and the fourth switch being interposed between the second plate of the capacitor and a voltage reference, wherein the self test function comprises the steps of i) operating the signal injector to produce a first signal representative of an out of range voltage for an expected voltage difference between the first and second input nodes, and using the signal to cause the at least one comparator to place its output in an error state, and to charge the capacitor to the out of range voltage, ii) isolating the capacitor from the signal injector and voltage reference, and connecting the capacitor between the first and second input nodes such that the voltage stored on the capacitor is overwritten by the voltage difference between the first and second nodes, and iii) and reconnecting the capacitor to the comparator and monitoring the comparator's output.

Monitoring circuit having a self test function

An analog to digital converter comprising at least two analog to digital conversion engines and a controller for controlling the operation of the analog to digital conversion engines such that during a first phase of an analog to digital conversion process the engines collaborate such that a plurality of bits can be determined during a single trial step; and during a second phase of the analog to digital conversion the conversion engines work independently; and the controller receives the outputs of at least one of the conversion engines and processes them to provide an output word.

Analog to digital converter

A method for placing a device in a selected mode of operation. The method comprises the steps of initializing a device select signal into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first user-controlled time window. A device is also described that includes means for detecting logic state transitions at a device select input and a clock input, and means for changing operating mode of the device in response to a predetermined number of logic state transitions at the clock input, occurring between logic state transitions at the device select input. The selected operating mode may be a reduced power consumption mode, for example, or another operating mode of the device, such as a daisy-chain mode of operation, or a mode that accommodates programming of analog input range.

Method for placing a device in a selected mode of operation

A test mode control circuit for reconfiguring a device pin of an integrated circuit chip which is initially configured in a test mode includes an input register for applying trim/configuring data to one or more components on an integrated circuit chip; a device pin; an output register for receiving output data from an integrated circuit on an integrated circuit chip which integrated circuit has had one or more of its elements trimmed/reconfigured; an I/O logic circuit for controlling the device pin to operate as a test pin to selectively deliver the trim/configuring data to the input register and receive output data form the output register; a programmable ray including a plurality of logic state elements for permanently mapping a selected set of the trim/configuring data from the input register, the programmable array including a test bit; and a switching system for applying the trim/configuring data to the one or more components on the integrated circuit when the test bit is in a first, test mode and for applying the permanently mapped trim/configuring data to the components in a second, normal mode.

Test mode control circuit for reconfiguring a device pin of an integrated circuit chip

A voltage boost circuit includes a boost capacitor; a charge circuit for charging in the charging mode the boost capacitor to a supply voltage, the charging circuit including a charging MOS switch interconnected between the supply voltage and one terminal of the boost capacitor and a back gate isolation circuit connected to the back gate of the charging MOS switch and including a first switch for connecting the back gate to the supply voltage for reverse biasing the back gate in the charging mode and the second switch for connecting the back gate to the one terminal of the boost capacitor for reverse biasing the back gate in the boost mode to prevent charge loss from the boost capacitor; and a boost bias voltage and a boost switch for connecting the second terminal of the boost capacitor to the boost bias voltage in the boost mode.

Voltage boost circuit and low supply voltage sampling switch circuit using same

A method for placing a device in a reduced power-consumption mode of operation. The method comprises the steps of initializing a device select signal into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first predetermined time window. A device is also described that includes means for detecting logic state transitions at a device select input and a clock input, and means for changing operating mode of the device in response to a predetermined number of logic state transitions at the clock input, occurring between logic state transitions at the device select input.

System and method to place a device in power down modes/states and restore back to first mode/state within user-controlled time window

An improved successive approximation analogue-to-digital converter system including a D/A converter and a comparison capability, wherein a first trial value is stored in a successive approximation register and a comparison is made of relative amplitude of D/A converter output with respect to analogue signal amplitude, and an iterative process is performed in which a subsequent trial value is stored in the successive approximation register before the comparison is repeated. The improvement comprises conducting only one comparison for each trial, with the subsequent trial value for a plurality of iterations being greater than one-half the first trial value, such that a first trial value determined in error is corrected during subsequent iterations. Apparatus implementing the improved successive approximation A/D is also described.

Successive approximation analogue-to-digital converter

An IC chip having an analog-to-digital converter together with control circuitry for effecting switchover between normal-power mode and low-power mode. The control circuitry includes a first D-type flip-flop with reset which receives on its 'D' input a continuous high signal; on its differential clock inputs the flip-flop receives complementary logic signals derived from the 'conversion start' (CONVST) signal applied to one pin of an 8-pin chip. In normal mode, the CONVST signal is a short pulse having an initial negative-going (falling) leading edge, and the flip-flop responds to that leading edge by producing a high Q output (CONVEN). This signals the A/D converter to carry out a conversion. In low-power mode, the CONVST short pulse is positive. The subsequent negative-going (falling) trailing edge of the pulse activates the flip-flop to cause its Q output to go high and turn on the A/D converter. The control circuitry includes a second D-type flip-flop (this one with set) which receives on its D input the CONVST signal. The Q output. of the second flip-flop generates a mode switchover control signal (designated SLEEPB). During low-power mode, established by the use of positive-going CONVST pulses, the low CONVEN signal at the end of conversion clocks the second flip-flop to sample CONVST on its D input, thereby causing the Q output of the second flip-flop (SLEEPB) to go low and switch the A/D converter into low-power status.

Analog-to-digital converter with optional low-power mode

An improved back gate switched sample and hold circuit includes a sample and hold channel including a sample switch having a back gate and a storage element; a back gate circuit for controlling the back gate of the sample switch; and a first attenuator circuit for scaling the input signal from a low impedance source for delivery to the sample switch and a second attenuator circuit responsive to the input signal from the low impedance source to independently drive the back gate circuit and isolate any distortion of the input signal in the back gate circuit from affecting the input signal in said sample and hold channel.

Back gate switched sample and hold circuit

A charge pump circuit for providing a bipolar output that substantially doubles the unipolar voltage input by utilizing a three-phase clock signal to charge a first capacitor in response to the first phase of the three-phase clock signal, then in response to either the second or third phase of the clock signal connect the first capacitor in series between the positive voltage input terminal and positive voltage output terminal to generate an output voltage which is positive in polarity and substantially double the voltage of the input source, then in response to the other of the second and third clock phases connect, between the input terminals, the first and second capacitors in series for providing a second polarity voltage across the second capacitor which is substantially double the source voltage and during either the following first or second clock pulse connect the second capacitor with its positive electrode connected to the negative input terminal and its negative electrode connected to the negative output terminal, thereby providing an output voltage which is negative in polarity and substantially double the voltage of the input source.

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Newbury, United Kingdom

Colin Charles Price