Interactic Holdings, LLC

Other

National Security Agency

The United States of America As Represented by the National Security Agency

Interactic Holding, LLC

Interactics Holdings, LLC

Denny, Ronald R.

Devany, Reed

Murphy, David

Reed, Coke S.

Ives, Michael R.

Coke S Reed

David P Murphy

John E Hesse

Michael Richard Ives

Ronald R Denny

Jay W Rockstroh

Ron Denny

Reed Devany

Thaine Hock

David Murphy

Michael R Ives

Embodiments of an interconnect apparatus enable improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. In an interconnect apparatus for core arrays a sending processing core can send data to a receiving core by forming a packet whose header indicates the location of the receiving core and whose pay load is the data to be sent. The packet is sent to a Data Vortex switch described herein and in the patents incorporated herein. The Data Vortex switch is on the same chip as an array of processing cores and routes the packet to the receiving core first by routing the packet to the processing core array containing the receiving processing core. The Data Vortex switch then routes the packet to the receiving processor core in a processor core array. Since the Data Vortex switches are not crossbar switches, there is no need to globally set and reset the Data Vortex switches as different groups of packets enter the switches. Mounting the Data Vortex switch on the same chip as the array of processing cores reduces the power required and reduces latency.

Method and apparatus for improved data transfer between processor cores

An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD. For a packet PKT divided into subpackets, a subpacket of the packet PKT at the logic unit LA, and the packet specifying a target either: (A) the logic unit LC sends a subpacket of the packet PKT to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD; (B) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA sends a subpacket of the packet PKT to the logic unit LD; or (C) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD.

Parallel data switch

Techniques are disclosed relating to parallel computing. In some embodiments, fine-grained data communication facilitates operations on large data sets such as multiplication of a sparse matrix by a vector. In this example, a first data set (the matrix) and a second data set (the vector) are distributed across multiple processing nodes. Performance of the overall multiplication operation may require communication of data among the processing nodes. In various embodiments, fine-grained communication of this data may reduce processing times and/or power consumption by avoiding congestion.

Matrix vector multiply techniques

Embodiments of a data handling apparatus can include a network interface controller configured to interface a processing node to a network. The network interface controller can include a network interface, a register interface, a processing node interface, and logic. The network interface can include lines coupled to the network for communicating data on the network. The register interface can include lines coupled to multiple registers. The processing node interface can include at least one line coupled to the processing node for communicating data with a local processor local to the processing node wherein the local processor can read data to and write data from the registers. The logic can receive packets including a header and a payload from the network and can insert the packets into the registers as indicated by the header.

Parallel information system utilizing flow control and virtual channels

A network device comprises a controller that manages data flow through a network interconnecting a plurality of processors. The processors of the processor plurality comprise a local memory divided into a private local memory and a public local memory, a local cache, and working registers. The network device further comprises a plurality of cache mirror registers coupled to the controller that receive data to be forwarded to the processor plurality. The controller is responsive to a request to receive data by transferring requested data directly to public memory without interrupting the processor, and by transferring requested data via at least one cache mirror register for a transfer to processor local cache, and to processor working registers.

Network interface for use in parallel computing systems

In a system, a memory controller separates a memory into multiple banks and enables a plurality of selected banks to be accessed concurrently. The memory controller further comprises a logic that creates a representation of a tree structure in memory and builds routing tables accessed by pointers at nodes in the tree memory structure, and a logic that finds a target memory address based on a received Internet Protocol (IP) address used by the tree memory structure and the routing table.

Scalable distributed parallel access memory systems with internet routing applications

Network interface card for use in parallel computing systems

A switching system for routing information packets that can simultaneously receive a variety of packet formats. The packet formats include electronic packet transmissions, optical wave division multiplexed data (WDM) with a single frame consisting of a plurality of packets to be sent to a common output line, with each packet traveling on a separate wavelength, WDM packets where the header of an individual packet travels on a wavelength different from the remainder of the packet (i.e. the payload) and the payload either travels on a single wavelength or is subdivided into a plurality of sub-packets with each sub-packet carried on a separate wavelength, and the like. The system includes input devices, a scheduling unit, a switching unit; and variable delay line units. A deconcentrator in the packet switching system creates a minimum gap between packets.

Means and apparatus for a scaleable congestion free switching system with intelligent control III

A network or interconnect structureutilizes a data flow technique that is based on timing and positioning of messages communicating through the interconnect structure. Switching control is distributed throughout multiple nodesin the structure so that a supervisory controller providing a global control function and complex logic structures are avoided. The interconnect structure operates as a 'deflection' or 'hot potato' system in which processing and storage overhead at each node is minimized. Elimination of a global controller and buffering at the nodes greatly reduces the amount of control and logic structures in the interconnect structure, simplifying overall control components and network interconnect componentsand improving speed performance of message communication.

Multiple level minimum logic network

An interconnect structure comprises a logic capable of error detection and/or error correction. A logic formats a data stream into a plurality of fixed-size segments. The individual segments include a header containing at least a set presence bit and a target address, a payload containing at least segment data and a copy of the target address, and a parity bit designating parity of the payload, the logic arranging the segment plurality into a multiple-dimensional matrix. A logic analyzes segment data in a plurality of dimensions following passage of the data through a plurality of switches including analysis to detect segment error, column error, and payload error.

Highly parallel switching systems utilizing error correction

A network or interconnect structure which includes a plurality of nodes which are interconnected within a hierarchical multiple level structure. The level of each node is determined by the position of the node within the structure and data messages move from node to node from a source level to a destination level. Each node within the interconnect structure is capable of receiving simultaneous data messages at its input ports from any other node and the receiving node is able to transmit each of the received data messages through its output ports to separate nodes in the interconnect structure to one or more levels below the level of the receiving node.

Scalable apparatus and method for increasing throughput in multiple level minimum logic networks using a plurality of control lines

An interconnection network has a first stage network and a second stage network and a collection of devices outside the network so that a first device is capable of sending data to a second device. The first stage network is connected to inputs of the second stage network. The first and second stage networks each have more outputs than inputs. The data is first sent from the first device to the first stage network and then from the first stage network to the second stage network. The data is sent to the second device from the second stage network. The number of inputs to a device from the second stage network exceeds the number of outputs from a device into the first stage network. The latency through the entire system may be a fixed constant.

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Austin, TX, United States of America

Coke S Reed