Nvidia Corporation

Cody J Robson

Rouslan Lyubomirov Dimitrov

Sau Yan Keith Li

Lars Nordskog

Seth P Schneider

Gerrit Ary Slavenburg

Tom J Verbeure

Morgan Samuel McGuire

Charles N Hansen

Josef Bo Spjut

Joohwan Kim

Benjamin Boudaoud

A weighted average execution time associated with each execution stage of a plurality of execution stages used to process a plurality of frames in parallel is obtained. The processing of each of the plurality of frames is performed at each of the plurality of execution stages in a sequential order, starting with an initial execution stage and continuing with each subsequent execution stage. A first largest weighted average execution time associated with one of the plurality of execution stages is determined. A delay to the initial execution stage prior to processing a first next frame is applied. The delay is determined based on the first largest weighted average execution time.

Dynamically reducing latency in processing pipelines

A display device for measuring the end-to-end latency of a computing system. The computing system includes an input device, a computing device, and the display device. The display device is directly connected with the input device and receives input data packets generated by the input device in response to received user input events. The display device passes the input packets to the computing device for graphics processing. The display device measures the end-to-end latency comprising the sum of three latencies. A first latency comprises an input delay of the input device. A second latency comprises an amount of time between generation of the input packet and a corresponding change in pixel values caused by the input event at the display device. A third latency comprises a display latency. The display device also displays latency information associated with the measured end-to-end latency.

System-latency-aware display device

Growing community of inventors

San Jose, CA, United States of America

Cody J Robson